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Fri, 13 Dec 2024 14:14:53 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-303441e0f43sm413451fa.125.2024.12.13.14.14.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Dec 2024 14:14:51 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 14 Dec 2024 00:14:23 +0200 Subject: [PATCH 07/35] drm/msm/dpu: inline _setup_dspp_ops() Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241214-dpu-drop-features-v1-7-988f0662cb7e@linaro.org> References: <20241214-dpu-drop-features-v1-0-988f0662cb7e@linaro.org> In-Reply-To: <20241214-dpu-drop-features-v1-0-988f0662cb7e@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1344; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=TzajbLeXFeWcm21J+7IjoKJq84HYxMWKTI0BXOLnjkU=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnXLHE44BVGOKLQjlDQFY3advOwvZSm2J1OY1AG XfXgAAhpt+JATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ1yxxAAKCRCLPIo+Aiko 1aB7B/sH1wn/y7qCaV6CgPzDrhgCQVXvSEKI+LBsjMOQYP75lbHYEr5Xf02HQQT2TTUbDIdlcss vbOsD+bmAYfX4pZyK6AwVZBDs2k4dwqEfCrLI9jeYK7qUi0jdmqe147Y+Dm3Gy2kncoK8+9G/Yk LFfWe/jMiGbDPZ7XO5NV/nlkCjyzdo2onOe5xNoeRZEeqSZJf1K5oF1RrcI4GUdGuKJLIHq9pfu l9xURiyRwvJh/avQhfKCd7uuEr2gBtKv8yJ0mFqe1GhtQhMGGFSeML5LZPEKhpGnPrMjjsbPf9k sB12UeoRn967bJoMGYGzj3XCLkKw9uj7wXC37YgWfuPMZDGU X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Inline the _setup_dspp_ops() function, it makes it easier to handle different conditions involving DSPP configuration. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c index 829ca272873e45b122c04bea7da22dc569732e10..0f5a74398e66642fba48c112db41ffc75ae2a79f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c @@ -63,13 +63,6 @@ static void dpu_setup_dspp_pcc(struct dpu_hw_dspp *ctx, DPU_REG_WRITE(&ctx->hw, base, PCC_EN); } -static void _setup_dspp_ops(struct dpu_hw_dspp *c, - unsigned long features) -{ - if (test_bit(DPU_DSPP_PCC, &features)) - c->ops.setup_pcc = dpu_setup_dspp_pcc; -} - /** * dpu_hw_dspp_init() - Initializes the DSPP hw driver object. * should be called once before accessing every DSPP. @@ -97,7 +90,8 @@ struct dpu_hw_dspp *dpu_hw_dspp_init(struct drm_device *dev, /* Assign ops */ c->idx = cfg->id; c->cap = cfg; - _setup_dspp_ops(c, c->cap->features); + if (test_bit(DPU_DSPP_PCC, &c->cap->features)) + c->ops.setup_pcc = dpu_setup_dspp_pcc; return c; }