From patchwork Wed Dec 18 10:26:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prashanth K X-Patchwork-Id: 852120 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C11371ACED2; Wed, 18 Dec 2024 10:28:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734517702; cv=none; b=QEQrYSJCy72AmiHm8ydKAKu71KBdeDKLtNSrJSaMz8HOAQojkulU4p9REdvqNx2XMN/od3SHBK+0s+ZKHpw7jv53XVcZGvGFXatGTW062HEMVSwNTr+E9Fx5wyS8bNSCs37HgcCmwYxuqS82+LkQ+tUjJh/pY5eyZN/+RbZqTRM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734517702; c=relaxed/simple; bh=C0CogyNIhxTky9adiPBl9g5pxuGsa62v+iKxRq98jTM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ch894pjygGP5Sgmzo9j2lXLhvPBTNYMP0XJlChDT5qgCaEWoy+jWZyHQj4wpSXd7DP/ujkVcNNsB6mPoYzqcOygKE0BgWbKoC3wJCVsGA2uhVkRCkodzdNWiGupmXOV7VqXQw1MOO97B1nW1glFdSsmcUl7IIATjm5bc6hz2084= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=RN7D6qL2; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="RN7D6qL2" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4BI4YLsN004217; Wed, 18 Dec 2024 10:28:17 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= Mn3H87iiQv5Svx4sJ6ohYM5FxSkAOiYiPnqQv5PMWpc=; b=RN7D6qL2g9ZGK3oM tpWDIcXApqjfM3ldEhFwdJwZf43cjIoAkZUOHKY7OOjNAc0o2Cs93GtuRBM7Qwhe wXNhnRRZg14EgWPUPKTIyWJawJiYiSiquaFLGLET9slkPIqQlgc69r0QOFNlOWul 2AxH6gJXrhFwx3jeUBTI2E9zDoX9tl/CHH4nvT9CzKgC7r7ItIQrV4ENNatKNX2Z +ki1Od0ygFlvu0YidYM59JrQG3zbcvYS2FKL0/Nm2y+IQuUm1B/n0vXYVNGNiCVN IbE9qu1KpGuNwppAWkHhXseGVsfa2a38sImRWRpwXasww642ENmp8dMwkT+PKlEF WhY/CQ== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43kqfsrt5j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 18 Dec 2024 10:28:17 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BIASGtQ012917 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 18 Dec 2024 10:28:16 GMT Received: from hu-prashk-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 18 Dec 2024 02:28:12 -0800 From: Prashanth K To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Kurapati CC: , , , , Prashanth K Subject: [PATCH v3 10/19] arm64: dts: qcom: Disable USB U1/U2 entry for SDM845 Date: Wed, 18 Dec 2024 15:56:58 +0530 Message-ID: <20241218102707.76272-11-quic_prashk@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20241218102707.76272-1-quic_prashk@quicinc.com> References: <20241218102707.76272-1-quic_prashk@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: UAsB7Ojq-abJh4sv-RTc-4b9yZUedreQ X-Proofpoint-ORIG-GUID: UAsB7Ojq-abJh4sv-RTc-4b9yZUedreQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=463 bulkscore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 malwarescore=0 phishscore=0 impostorscore=0 adultscore=0 mlxscore=0 suspectscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412180084 Disable U1 and U2 power-saving states to improve stability of USB. These low-power link states, designed to reduce power consumption during idle periods, can cause issues in latency-sensitive or high throughput use cases. Over the years, some of the issues seen are as follows: 1. In device mode of operation, when UVC is active, enabling U1/U2 is sometimes causing packets drops due to delay in entry/exit of intermittent these low power states. These packet drops are often reflected as missed isochronous transfers, as the controller wasn't able to send packet in that microframe interval and hence glitches are seen on the final transmitted video output. 2. On older targets like SM8150/SM8250/SM8350, there have been throughput issues seen during tethering use cases. Disabling these intermittent power states enhances device stability without affecting power usage. Signed-off-by: Prashanth K --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 1ed794638a7c..373a591bfb4d 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4139,6 +4139,8 @@ usb_1_dwc3: usb@a600000 { snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; snps,parkmode-disable-ss-quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; phy-names = "usb2-phy", "usb3-phy"; @@ -4215,6 +4217,8 @@ usb_2_dwc3: usb@a800000 { snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; snps,parkmode-disable-ss-quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; phy-names = "usb2-phy", "usb3-phy"; };