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Mon, 23 Dec 2024 09:03:13 GMT Received: from hu-renjiang-sha.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 23 Dec 2024 01:03:10 -0800 From: Renjiang Han Date: Mon, 23 Dec 2024 14:32:41 +0530 Subject: [PATCH v2 1/2] clk: qcom: videocc: Use HW_CTRL_TRIGGER flag for video GDSC's Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241223-switch_gdsc_mode-v2-1-eb5c96aee662@quicinc.com> References: <20241223-switch_gdsc_mode-v2-0-eb5c96aee662@quicinc.com> In-Reply-To: <20241223-switch_gdsc_mode-v2-0-eb5c96aee662@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Stanimir Varbanov , Vikash Garodia , Bryan O'Donoghue , Mauro Carvalho Chehab CC: , , , , Renjiang Han , Taniya Das X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1734944586; l=4173; i=quic_renjiang@quicinc.com; s=20241001; h=from:subject:message-id; bh=COVRZISqydMb46UZhxsQtad2I7Z2yboPPDC+0GyVIs4=; b=V2xYuazjdGQiBGJecUvHiK+fcif0+SQQa3BEgnLLS5MdXLb+ggGGM1l/5NRk0nRcnPC/iCjh5 Yg4kPUOKWcAAJTaOtUkQkdYh5QidtGg0QwCnQiwZ8aXShOXecNiyD3l X-Developer-Key: i=quic_renjiang@quicinc.com; a=ed25519; pk=8N59kMJUiVH++5QxJzTyHB/wh/kG5LxQ44j9zhUvZmw= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 86CUvkPw9n33Sa2rm1NaIOLhyM48fAeU X-Proofpoint-GUID: 86CUvkPw9n33Sa2rm1NaIOLhyM48fAeU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 bulkscore=0 phishscore=0 mlxscore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 priorityscore=1501 adultscore=0 mlxlogscore=679 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412230081 From: Taniya Das The video driver will be using the newly introduced dev_pm_genpd_set_hwmode() API to switch the video GDSC to HW and SW control modes at runtime. Hence use HW_CTRL_TRIGGER flag instead of HW_CTRL for video GDSC's for Qualcomm SoC SC7180, SDM845, SM7150, SM8150 and SM8450. Signed-off-by: Taniya Das Signed-off-by: Renjiang Han Reviewed-by: Dmitry Baryshkov --- drivers/clk/qcom/videocc-sc7180.c | 2 +- drivers/clk/qcom/videocc-sdm845.c | 4 ++-- drivers/clk/qcom/videocc-sm7150.c | 4 ++-- drivers/clk/qcom/videocc-sm8150.c | 4 ++-- drivers/clk/qcom/videocc-sm8450.c | 4 ++-- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/clk/qcom/videocc-sc7180.c b/drivers/clk/qcom/videocc-sc7180.c index d7f84548039699ce6fdd7c0f6675c168d5eaf4c1..dd2441d6aa83bd7cff17deeb42f5d011c1e9b134 100644 --- a/drivers/clk/qcom/videocc-sc7180.c +++ b/drivers/clk/qcom/videocc-sc7180.c @@ -166,7 +166,7 @@ static struct gdsc vcodec0_gdsc = { .pd = { .name = "vcodec0_gdsc", }, - .flags = HW_CTRL, + .flags = HW_CTRL_TRIGGER, .pwrsts = PWRSTS_OFF_ON, }; diff --git a/drivers/clk/qcom/videocc-sdm845.c b/drivers/clk/qcom/videocc-sdm845.c index f77a0777947773dc8902c92098acff71b9b8f10f..6dedc80a8b3e18eca82c08a5bcd7e1fdc374d4b5 100644 --- a/drivers/clk/qcom/videocc-sdm845.c +++ b/drivers/clk/qcom/videocc-sdm845.c @@ -260,7 +260,7 @@ static struct gdsc vcodec0_gdsc = { }, .cxcs = (unsigned int []){ 0x890, 0x930 }, .cxc_count = 2, - .flags = HW_CTRL | POLL_CFG_GDSCR, + .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR, .pwrsts = PWRSTS_OFF_ON, }; @@ -271,7 +271,7 @@ static struct gdsc vcodec1_gdsc = { }, .cxcs = (unsigned int []){ 0x8d0, 0x950 }, .cxc_count = 2, - .flags = HW_CTRL | POLL_CFG_GDSCR, + .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR, .pwrsts = PWRSTS_OFF_ON, }; diff --git a/drivers/clk/qcom/videocc-sm7150.c b/drivers/clk/qcom/videocc-sm7150.c index 14ef7f5617537363673662adc3910ddba8ea6a4f..b6912560ef9b7a84e7fd1d9924f5aac6967da780 100644 --- a/drivers/clk/qcom/videocc-sm7150.c +++ b/drivers/clk/qcom/videocc-sm7150.c @@ -271,7 +271,7 @@ static struct gdsc vcodec0_gdsc = { }, .cxcs = (unsigned int []){ 0x890, 0x9ec }, .cxc_count = 2, - .flags = HW_CTRL | POLL_CFG_GDSCR, + .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR, .pwrsts = PWRSTS_OFF_ON, }; @@ -282,7 +282,7 @@ static struct gdsc vcodec1_gdsc = { }, .cxcs = (unsigned int []){ 0x8d0, 0xa0c }, .cxc_count = 2, - .flags = HW_CTRL | POLL_CFG_GDSCR, + .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR, .pwrsts = PWRSTS_OFF_ON, }; diff --git a/drivers/clk/qcom/videocc-sm8150.c b/drivers/clk/qcom/videocc-sm8150.c index daab3237eec19b727d34512d3a2ba1d7bd2743d6..3024f6fc89c8b374f2ef13debc283998cb136f6b 100644 --- a/drivers/clk/qcom/videocc-sm8150.c +++ b/drivers/clk/qcom/videocc-sm8150.c @@ -179,7 +179,7 @@ static struct gdsc vcodec0_gdsc = { .pd = { .name = "vcodec0_gdsc", }, - .flags = HW_CTRL, + .flags = HW_CTRL_TRIGGER, .pwrsts = PWRSTS_OFF_ON, }; @@ -188,7 +188,7 @@ static struct gdsc vcodec1_gdsc = { .pd = { .name = "vcodec1_gdsc", }, - .flags = HW_CTRL, + .flags = HW_CTRL_TRIGGER, .pwrsts = PWRSTS_OFF_ON, }; static struct clk_regmap *video_cc_sm8150_clocks[] = { diff --git a/drivers/clk/qcom/videocc-sm8450.c b/drivers/clk/qcom/videocc-sm8450.c index f26c7eccb62e7eb8dbd022e2f01fa496eb570b3f..4cefcbbc020f201f19c75c20229415e0bdea2963 100644 --- a/drivers/clk/qcom/videocc-sm8450.c +++ b/drivers/clk/qcom/videocc-sm8450.c @@ -347,7 +347,7 @@ static struct gdsc video_cc_mvs0_gdsc = { }, .pwrsts = PWRSTS_OFF_ON, .parent = &video_cc_mvs0c_gdsc.pd, - .flags = RETAIN_FF_ENABLE | HW_CTRL, + .flags = HW_CTRL_TRIGGER | RETAIN_FF_ENABLE, }; static struct gdsc video_cc_mvs1c_gdsc = { @@ -372,7 +372,7 @@ static struct gdsc video_cc_mvs1_gdsc = { }, .pwrsts = PWRSTS_OFF_ON, .parent = &video_cc_mvs1c_gdsc.pd, - .flags = RETAIN_FF_ENABLE | HW_CTRL, + .flags = HW_CTRL_TRIGGER | RETAIN_FF_ENABLE, }; static struct clk_regmap *video_cc_sm8450_clocks[] = {