| Message ID | 20250203-b4-branch-gfx-smmu-v4-2-eaa7aa762f48@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for GPU SMMU on QCS8300 | expand |
Hi Can someone kindly review this patch?
On 2/10/2025 4:31 PM, Dmitry Baryshkov wrote: > On Mon, Feb 03, 2025 at 11:17:02AM +0530, Pratyush Brahma wrote: >> Add the device node for gfx smmu that is required for gpu >> specific address translations. >> >> Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 39 +++++++++++++++++++++++++++++++++++ >> 1 file changed, 39 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi >> index 4a057f7c0d9fae0ebd1b3cf3468746b382bc886b..7a8211bec139375b5aab939f123d88fca7aceff2 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi >> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi >> @@ -2674,6 +2674,45 @@ gpucc: clock-controller@3d90000 { >> #power-domain-cells = <1>; >> }; >> >> + adreno_smmu: iommu@3da0000 { >> + compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu", >> + "qcom,smmu-500", "arm,mmu-500"; >> + reg = <0x0 0x3da0000 0x0 0x20000>; >> + #iommu-cells = <2>; >> + #global-interrupts = <2>; >> + >> + interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, >> + <&gpucc GPU_CC_HUB_CX_INT_CLK>, >> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, >> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, >> + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, >> + <&gpucc GPU_CC_AHB_CLK>, >> + <&gpucc GPU_CC_HUB_AON_CLK>; >> + >> + clock-names = "gcc_gpu_memnoc_gfx_clk", > Stray whitespace after the Tab symbol > >> + "gcc_gpu_snoc_dvm_gfx_clk", >> + "gpu_cc_ahb_clk", >> + "gpu_cc_hlos1_vote_gpu_smmu_clk", >> + "gpu_cc_cx_gmu_clk", >> + "gpu_cc_hub_cx_int_clk", >> + "gpu_cc_hub_aon_clk"; > clocks and clock-names do not match. > >> + power-domains = <&gpucc GPU_CC_CX_GDSC>; >> + dma-coherent; >> + }; >> + >> pmu@9091000 { >> compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; >> reg = <0x0 0x9091000 0x0 0x1000>; >> >> -- >> 2.34.1 >> Thanks for checking. Will address these in next version.
On 10/02/2025 12:41, Krzysztof Kozlowski wrote: > On 10/02/2025 05:58, Pratyush Brahma wrote: >> Hi >> >> Can someone kindly review this patch? >> > > After 7 days? Community is not working for you to make such demands. > Observe standard waiting time. Or better: Please relax, and help out by > reviewing other patches on the mailing lists in order to relieve the > burden of maintainers and move your patches higher up the list. Before you start pinging us, test your patches. That's one of the easiest steps to get your patches reviewed or applied fast. Best regards, Krzysztof
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 4a057f7c0d9fae0ebd1b3cf3468746b382bc886b..7a8211bec139375b5aab939f123d88fca7aceff2 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -2674,6 +2674,45 @@ gpucc: clock-controller@3d90000 { #power-domain-cells = <1>; }; + adreno_smmu: iommu@3da0000 { + compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x3da0000 0x0 0x20000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + + interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>; + + clock-names = "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk", + "gpu_cc_hlos1_vote_gpu_smmu_clk", + "gpu_cc_cx_gmu_clk", + "gpu_cc_hub_cx_int_clk", + "gpu_cc_hub_aon_clk"; + power-domains = <&gpucc GPU_CC_CX_GDSC>; + dma-coherent; + }; + pmu@9091000 { compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; reg = <0x0 0x9091000 0x0 0x1000>;
Add the device node for gfx smmu that is required for gpu specific address translations. Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com> --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 39 +++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+)