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Mon, 3 Feb 2025 05:47:30 GMT Received: from hu-pbrahma-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 2 Feb 2025 21:47:26 -0800 From: Pratyush Brahma Date: Mon, 3 Feb 2025 11:17:02 +0530 Subject: [PATCH v4 2/2] arm64: dts: qcom: qcs8300: Add device node for gfx_smmu Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250203-b4-branch-gfx-smmu-v4-2-eaa7aa762f48@quicinc.com> References: <20250203-b4-branch-gfx-smmu-v4-0-eaa7aa762f48@quicinc.com> In-Reply-To: <20250203-b4-branch-gfx-smmu-v4-0-eaa7aa762f48@quicinc.com> To: Will Deacon , Robin Murphy , "Joerg Roedel" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio CC: , , , , , Pratyush Brahma X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1738561638; l=2222; i=quic_pbrahma@quicinc.com; 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Signed-off-by: Pratyush Brahma --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 39 +++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 4a057f7c0d9fae0ebd1b3cf3468746b382bc886b..7a8211bec139375b5aab939f123d88fca7aceff2 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -2674,6 +2674,45 @@ gpucc: clock-controller@3d90000 { #power-domain-cells = <1>; }; + adreno_smmu: iommu@3da0000 { + compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x3da0000 0x0 0x20000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>; + + clock-names = "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk", + "gpu_cc_hlos1_vote_gpu_smmu_clk", + "gpu_cc_cx_gmu_clk", + "gpu_cc_hub_cx_int_clk", + "gpu_cc_hub_aon_clk"; + power-domains = <&gpucc GPU_CC_CX_GDSC>; + dma-coherent; + }; + pmu@9091000 { compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; reg = <0x0 0x9091000 0x0 0x1000>;