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Wed, 5 Feb 2025 14:31:42 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 44hcpm8b4a-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 05 Feb 2025 14:31:42 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 515EVfgP026606; Wed, 5 Feb 2025 14:31:41 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-msavaliy-hyd.qualcomm.com [10.213.110.207]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 515EVfeF026605 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 05 Feb 2025 14:31:41 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 429934) id 425BC2439F; Wed, 5 Feb 2025 20:01:41 +0530 (+0530) From: Mukesh Kumar Savaliya To: alexandre.belloni@bootlin.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, jarkko.nikula@linux.intel.com, linux-i3c@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mukesh Kumar Savaliya Subject: [PATCH v1 1/3] dt-bindings: i3c: Add Qualcomm I3C master controller bindings Date: Wed, 5 Feb 2025 20:01:07 +0530 Message-Id: <20250205143109.2955321-2-quic_msavaliy@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250205143109.2955321-1-quic_msavaliy@quicinc.com> References: <20250205143109.2955321-1-quic_msavaliy@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Cg86Oyt46s-s-XFp5yekzxyngKR0fd-F X-Proofpoint-GUID: Cg86Oyt46s-s-XFp5yekzxyngKR0fd-F X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-05_06,2025-02-05_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 mlxscore=0 impostorscore=0 suspectscore=0 mlxlogscore=999 bulkscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 spamscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502050114 Add device tree bindings for the Qualcomm I3C master controller. This includes the necessary documentation and properties required to describe the hardware in the device tree. Signed-off-by: Mukesh Kumar Savaliya --- .../bindings/i3c/qcom,i3c-master.yaml | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/i3c/qcom,i3c-master.yaml diff --git a/Documentation/devicetree/bindings/i3c/qcom,i3c-master.yaml b/Documentation/devicetree/bindings/i3c/qcom,i3c-master.yaml new file mode 100644 index 000000000000..ad63ea779fd6 --- /dev/null +++ b/Documentation/devicetree/bindings/i3c/qcom,i3c-master.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i3c/qcom,i3c-master.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm I3C master controller + +maintainers: + - Mukesh Kumar Savaliya + +allOf: + - $ref: i3c.yaml# + +properties: + compatible: + const: qcom,geni-i3c + + reg: + minItems: 1 + maxItems: 2 + + clocks: + minItems: 1 + + clock-names: + items: + - const: se-clk + + interrupts-extended: + minItems: 1 + maxItems: 3 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts-extended + +unevaluatedProperties: false + +examples: + - | + #include + #include + + i3c@884000 { + compatible = "qcom,geni-i3c"; + reg = <0x00884000 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se-clk"; + interrupts-extended = <&intc GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <0>; + }; +...