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Wed, 5 Feb 2025 18:28:21 GMT Received: from c194c8e2f407.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 5 Feb 2025 10:28:17 -0800 From: Raviteja Laggyshetty To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio CC: Odelu Kukatla , Mike Tipton , Jeff Johnson , "Andrew Halaney" , Sibi Sankar , , , , Subject: [PATCH V8 3/7] interconnect: qcom: Add multidev EPSS L3 support Date: Wed, 5 Feb 2025 18:27:39 +0000 Message-ID: <20250205182743.915-4-quic_rlaggysh@quicinc.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250205182743.915-1-quic_rlaggysh@quicinc.com> References: <20250205182743.915-1-quic_rlaggysh@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: GC3RFZHm9o6tSrkfQ7AEmZAvdFhulNTD X-Proofpoint-ORIG-GUID: GC3RFZHm9o6tSrkfQ7AEmZAvdFhulNTD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-05_06,2025-02-05_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 clxscore=1015 suspectscore=0 mlxlogscore=999 impostorscore=0 mlxscore=0 spamscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502050141 EPSS on SA8775P has two instances, necessitating the creation of two device nodes with different compatibles due to the unique ICC node ID and name limitations in the interconnect framework. Add multidevice support for the OSM-L3 provider to dynamically obtain unique node IDs and register with the framework. Signed-off-by: Raviteja Laggyshetty --- drivers/interconnect/qcom/osm-l3.c | 46 +++++++++++++++++------------- 1 file changed, 26 insertions(+), 20 deletions(-) diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c index 6a656ed44d49..da2d82700b5a 100644 --- a/drivers/interconnect/qcom/osm-l3.c +++ b/drivers/interconnect/qcom/osm-l3.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -33,6 +34,7 @@ #define EPSS_REG_PERF_STATE 0x320 #define OSM_L3_MAX_LINKS 1 +#define ALLOC_DYN_ID -1 #define to_osm_l3_provider(_provider) \ container_of(_provider, struct qcom_osm_l3_icc_provider, provider) @@ -55,46 +57,40 @@ struct qcom_osm_l3_icc_provider { */ struct qcom_osm_l3_node { const char *name; - u16 links[OSM_L3_MAX_LINKS]; - u16 id; + struct qcom_osm_l3_node *links[OSM_L3_MAX_LINKS]; + int id; u16 num_links; u16 buswidth; }; struct qcom_osm_l3_desc { - const struct qcom_osm_l3_node * const *nodes; + struct qcom_osm_l3_node * const *nodes; size_t num_nodes; unsigned int lut_row_size; unsigned int reg_freq_lut; unsigned int reg_perf_state; }; -enum { - OSM_L3_MASTER_NODE = 10000, - OSM_L3_SLAVE_NODE, -}; - -#define DEFINE_QNODE(_name, _id, _buswidth, ...) \ - static const struct qcom_osm_l3_node _name = { \ +#define DEFINE_QNODE(_name, _buswidth, ...) \ + static struct qcom_osm_l3_node _name = { \ .name = #_name, \ - .id = _id, \ .buswidth = _buswidth, \ .num_links = COUNT_ARGS(__VA_ARGS__), \ .links = { __VA_ARGS__ }, \ } -DEFINE_QNODE(osm_l3_master, OSM_L3_MASTER_NODE, 16, OSM_L3_SLAVE_NODE); -DEFINE_QNODE(osm_l3_slave, OSM_L3_SLAVE_NODE, 16); +DEFINE_QNODE(osm_l3_slave, 16); +DEFINE_QNODE(osm_l3_master, 16, &osm_l3_slave); -static const struct qcom_osm_l3_node * const osm_l3_nodes[] = { +static struct qcom_osm_l3_node * const osm_l3_nodes[] = { [MASTER_OSM_L3_APPS] = &osm_l3_master, [SLAVE_OSM_L3] = &osm_l3_slave, }; -DEFINE_QNODE(epss_l3_master, OSM_L3_MASTER_NODE, 32, OSM_L3_SLAVE_NODE); -DEFINE_QNODE(epss_l3_slave, OSM_L3_SLAVE_NODE, 32); +DEFINE_QNODE(epss_l3_slave, 32); +DEFINE_QNODE(epss_l3_master, 32, &epss_l3_slave); -static const struct qcom_osm_l3_node * const epss_l3_nodes[] = { +static struct qcom_osm_l3_node * const epss_l3_nodes[] = { [MASTER_EPSS_L3_APPS] = &epss_l3_master, [SLAVE_EPSS_L3_SHARED] = &epss_l3_slave, }; @@ -164,7 +160,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) const struct qcom_osm_l3_desc *desc; struct icc_onecell_data *data; struct icc_provider *provider; - const struct qcom_osm_l3_node * const *qnodes; + struct qcom_osm_l3_node * const *qnodes; struct icc_node *node; size_t num_nodes; struct clk *clk; @@ -242,6 +238,10 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) icc_provider_init(provider); + /*Initialize IDs to ALLOC_DYN_ID to indicate dynamic id allocation*/ + for (i = 0; i < num_nodes; i++) + qnodes[i]->id = ALLOC_DYN_ID; + for (i = 0; i < num_nodes; i++) { size_t j; @@ -250,14 +250,19 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) ret = PTR_ERR(node); goto err; } + qnodes[i]->id = node->id; node->name = qnodes[i]->name; /* Cast away const and add it back in qcom_osm_l3_set() */ node->data = (void *)qnodes[i]; icc_node_add(node, provider); - for (j = 0; j < qnodes[i]->num_links; j++) - icc_link_create(node, qnodes[i]->links[j]); + for (j = 0; j < qnodes[i]->num_links; j++) { + struct qcom_osm_l3_node *link_node = qnodes[i]->links[j]; + + icc_link_create(node, link_node->id); + link_node->id = (node->links[node->num_links - 1])->id; + } data->nodes[i] = node; } @@ -278,6 +283,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) static const struct of_device_id osm_l3_of_match[] = { { .compatible = "qcom,epss-l3", .data = &epss_l3_l3_vote }, { .compatible = "qcom,osm-l3", .data = &osm_l3 }, + { .compatible = "qcom,sa8775p-epss-l3", .data = &epss_l3_perf_state }, { .compatible = "qcom,sc7180-osm-l3", .data = &osm_l3 }, { .compatible = "qcom,sc7280-epss-l3", .data = &epss_l3_perf_state }, { .compatible = "qcom,sdm845-osm-l3", .data = &osm_l3 },