From patchwork Thu Feb 6 12:18:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 863090 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E4E322DF93; Thu, 6 Feb 2025 12:18:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738844339; cv=none; b=u0lXquX6jq0C4qBnD6rLDUYWXdn8b2QHODB4H0NdxWlu8LOYtVQJ8Ymirfo+me0YC2H/maLEB8NYyudNgwzh4njpw1+h7g5t1ebl36wPkujh5XAXxlrF7RkOlY07J3mc4NXQ2MlY2ApqGEVSK5BjjdTVt8no9vtRBhShIrIQwG0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738844339; c=relaxed/simple; bh=sE2NbpIlUkdtO6tKcVVaL/NQC6wj6NV39nPEbZhvTSw=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=BZH35yXLJj/QSExA1v1RxsiyjZ+tVB72hESR90xDzvclQRkW3Sa0pRYFe6jlnzqR9b18myu3RctYQTnipcvZ27Gxo5O8nGhYULxQvwp16W+/ZqPeNfSAjikr9Lti0dewNHDOdfiva02ybpIhS5tvbj+zi3SUI7HvBB8YlhJ7NnY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=Hjj2Avpb; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Hjj2Avpb" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5169CQTi014655; Thu, 6 Feb 2025 12:18:49 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= SmnqKVEhul/G1MbtymvYm1LCXV4zDDH7X16zFx97Vn0=; b=Hjj2Avpbt0HKIarN BAE1BObNmUUkT6l+zFBvBOArkDJo8B+5cZtwWiHmVrSBHNycJTqdbwoErp82OIq/ so9yYCWLCKGlaXSBAbLpOwmYEeZCRxdwVdb35Y6qdD44ChWKYFcXOExt105VKCeL teRdZIm3Dh9TJuzOPqRoO6wyd2QjqqjrDv+JFUQlwnOGvlUiP4F/ZDnzYzeIGpxD 35HkLLk/FjAoNe7zcWgzsGzvNk2tqekX8NaNA3khDCBwAxf0AP8TkzV1aekHl/Ug K1kAVk47PBG6yhx94YNxuHTVDBoVwMDic2aacx0JILhQzWo97i3d5qLIbhOjZ0oI 9WuPDQ== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44mt8e0fjf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 06 Feb 2025 12:18:48 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 516CIm50019043 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 6 Feb 2025 12:18:48 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 6 Feb 2025 04:18:42 -0800 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v10 5/7] dt-bindings: PCI: qcom: Document the IPQ5332 PCIe controller Date: Thu, 6 Feb 2025 17:48:01 +0530 Message-ID: <20250206121803.1128216-6-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250206121803.1128216-1-quic_varada@quicinc.com> References: <20250206121803.1128216-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 5YYF2ZMPta81-ds9Ily-6K6T-p1Pi-3A X-Proofpoint-GUID: 5YYF2ZMPta81-ds9Ily-6K6T-p1Pi-3A X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-06_03,2025-02-05_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 adultscore=0 priorityscore=1501 impostorscore=0 mlxscore=0 spamscore=0 lowpriorityscore=0 suspectscore=0 mlxlogscore=999 malwarescore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502060102 Document the PCIe controller on IPQ5332 platform. IPQ5332 will use IPQ9574 as the fall back compatible. Signed-off-by: Varadarajan Narayanan Reviewed-by: Krzysztof Kozlowski --- v10: Remove unnecessary ipq5332 constraint in 'power domains' not required constraint Fix maxItems for interrupts contstraint of sdm845 v9: Remove superfluous ipq5332 constraint since the fallback is present v8: Use ipq9574 as fallback compatible for ipq5332 along with ipq5424 v7: Moved ipq9574 related changes to a separate patch Add 'global' interrupt v6: Commit message update only. Add info regarding the moving of ipq9574 from 5 "reg" definition to 5 or 6 reg definition. v5: Re-arrange 5332 and 9574 compatibles to handle fallback usage in dts v4: * v3 reused ipq9574 bindings for ipq5332. Instead add one for ipq5332 * DTS uses ipq9574 compatible as fallback. Hence move ipq9574 to be able to use the 'reg' section for both ipq5332 and ipq9574. Else, dtbs_check and dt_binding_check flag errors. --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 4b4927178abc..6696a36009da 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -33,6 +33,7 @@ properties: - qcom,pcie-sdx55 - items: - enum: + - qcom,pcie-ipq5332 - qcom,pcie-ipq5424 - const: qcom,pcie-ipq9574 - items: @@ -49,11 +50,11 @@ properties: interrupts: minItems: 1 - maxItems: 8 + maxItems: 9 interrupt-names: minItems: 1 - maxItems: 8 + maxItems: 9 iommu-map: minItems: 1 @@ -443,6 +444,7 @@ allOf: interrupts: minItems: 8 interrupt-names: + minItems: 8 items: - const: msi0 - const: msi1 @@ -452,6 +454,7 @@ allOf: - const: msi5 - const: msi6 - const: msi7 + - const: global - if: properties: @@ -599,6 +602,7 @@ allOf: - properties: interrupts: minItems: 8 + maxItems: 8 interrupt-names: items: - const: msi0