From patchwork Thu Feb 13 21:04:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anjelique Melendez X-Patchwork-Id: 865134 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EAB6126981C for ; Thu, 13 Feb 2025 21:04:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739480653; cv=none; b=fadexnzXUpu+huzE6a0Fk8l9mZpC+N2fm2D7CC9h7iL9zXR8uTYn0JlHybfUxqP6avr6dHpvYVR79hns2+JnNa6n5CtEwVT3ME2JJJMJgh9aTaTtXDh9kRwUb80fejEd+H9Kp+vj6uJrwtvStqIzWv/jhPmYIdzPw8bqbmKNiGM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739480653; c=relaxed/simple; bh=DecLmToxwMQkR8jL+PSo4Tt2J4g+s8DpyxCx4NCWX3Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Q455DefnI4uwLbyzeUUPouim3nMAJ03U5JJXSjCnfMPdv3hXn3eN5jCqBwJX2IfeTQpVfiU8P08uCTXL0kEZEo9e4I1GRYAK4iZDblW9AWmgpdssOzYck8bbKrR9nyclv1E88TsZiuNcCm+KJXZ7D7Ndg9vRbqMFYPCFsIUZ3NM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=YEr3JE7G; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="YEr3JE7G" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 51DAog47002493 for ; Thu, 13 Feb 2025 21:04:11 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=ix8czGogiPA veGuEM67krjF1GRJMfjhSqgWNw496tqY=; b=YEr3JE7G9y/Y7Zz5CTVFPkpHNeK Qtc4KiE/qjV5PKhd4OQI4CyQGyE7uwirlox2h+qXlqo6VBePpL6/9EFtgr5dmm2H 6KhqwGi2oKVysP1b/CoSdoEd9zSqjmecSS9YBvaROpEHKZj6EyPVTeLXvI+A6CTe kah6wuFFTMlMHid7v/pa9K4z3OZbZvi9UPVInpy1D7oBt28GATgJYgf2DvgOSfpC AgHKgu1RTHgISYtLI2egx3IZlCsY86V29Yc1KmBOZIjIMwhqq32VqhByFoTLvl4B w51k2PTJJZaR0DCYSi3SPMn8EixTygtsD2FV4r26fT0fOfcY2otmWjXzsbQ== Received: from mail-pl1-f197.google.com (mail-pl1-f197.google.com [209.85.214.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44s5w4b033-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Thu, 13 Feb 2025 21:04:10 +0000 (GMT) Received: by mail-pl1-f197.google.com with SMTP id d9443c01a7336-220e1593b85so14381165ad.3 for ; Thu, 13 Feb 2025 13:04:10 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739480650; x=1740085450; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ix8czGogiPAveGuEM67krjF1GRJMfjhSqgWNw496tqY=; b=tYOvyN/1iJHdQ/h3shl93GHOFCOGGO4Ixklsi9UYVSDlL2FM6TjYF7JumhfJmzmV/r Q8OzdBdoCYYRFdxCFJc0/oo2kbV0ISSXDERbzan0fKhQ7F2npIY48/0U0TbFeuMGDJX5 6ABa42VQKAp7OY6aE0UGaIdf+dWQf0lZOfO34XBAiMDLsG0tFJL7WwHdsaRywDKRlBnd ArYiL0s80cjYh+KAdunnn5ek8p5MygU7TGz9rP+Mdhw8lyOUgdY956ZUGBgtLqUZcDSv wPsL3u8t6ygweY0aPbRI7GJDmCsOiEqv/I9N2GE2V60tcxF6RWgeaStPtZ4lx+xF48/f 9cXw== X-Forwarded-Encrypted: i=1; AJvYcCV7G3sv6eLvy1FEZIrIFaOZKZJUr8FecMab9wvzM7lUy+bewsCx9T9d7hc2WvosFjwhadGfO1u+iJLFQMTj@vger.kernel.org X-Gm-Message-State: AOJu0YzFpkhuxygk1x517yfnDUsRYRNZgZE3CN2V7HuTpX0SPdmYg65S faaGxg61v1z2/BpxjEiR2C1gt3Sp/QO+Mlvq82jPaPud7gjAGkLd7ie2J9XELY6Kj6gaupzK1/y NatSnRUd8FQodhFQ1UnXjLTiHjd9lUsMAIglA8nQUNJeaFVd/g+6nZ0jkohgA3+DJ X-Gm-Gg: ASbGncv/ZapsqGK5G3KAL6x1TGOWiTIc+7Pa7aa5A8fudq+mYEj/xsEMkNNlznb1OCs LnA1oSwqMlpJMXIPQ0T8vOMHnpdxUNAlFMBm/35b3d2S0Uq1SmykFk+teNVzv+JxY+/RWxuC6qv KiFNBgEaPsSWBPKY1xgPwAhxU9yauRln37KHRkKYn7Q11eq6L3KCbpMc8Euc25VambqdQ1B8h5F KB/4Wit1P25SGOMmXy3C6FC5pPbEH5HF/azw3GlXJ4L/bU58q+ibjBNAieBXZtgd8PbkdPL7iZ1 ru5ZKMtGyxaaPL4zKvgC6sNRpiWra1UYAasTUNciPOfHRtz9+yeQwSO2kO1TfHx0ch5Q X-Received: by 2002:a17:903:290:b0:216:7ee9:220b with SMTP id d9443c01a7336-220d1eee443mr87217795ad.22.1739480649782; Thu, 13 Feb 2025 13:04:09 -0800 (PST) X-Google-Smtp-Source: AGHT+IGxiHWh5/198xxh/vHKG28dp2GWtimkNHpX9GPLIowPDihT48qdQifh6lQ3aKFPzNiGhGDi6g== X-Received: by 2002:a17:903:290:b0:216:7ee9:220b with SMTP id d9443c01a7336-220d1eee443mr87217315ad.22.1739480649332; Thu, 13 Feb 2025 13:04:09 -0800 (PST) Received: from hu-amelende-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-220dacfc769sm14339375ad.201.2025.02.13.13.04.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Feb 2025 13:04:09 -0800 (PST) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/4] thermal: qcom-spmi-temp-alarm: add support for LITE PMIC peripherals Date: Thu, 13 Feb 2025 13:04:03 -0800 Message-Id: <20250213210403.3396392-5-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250213210403.3396392-1-anjelique.melendez@oss.qualcomm.com> References: <20250213210403.3396392-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: 6kujnyFf0i9Pu7YgkeGSU7xOcATKdqKW X-Proofpoint-ORIG-GUID: 6kujnyFf0i9Pu7YgkeGSU7xOcATKdqKW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-13_08,2025-02-13_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 mlxlogscore=999 priorityscore=1501 adultscore=0 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502130148 Add support for TEMP_ALARM LITE PMIC peripherals. This subtype utilizes a pair of registers to configure a warning interrupt threshold temperature and an automatic hardware shutdown threshold temperature. Signed-off-by: David Collins Signed-off-by: Anjelique Melendez --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 204 +++++++++++++++++++- 1 file changed, 203 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c index a10f368f2039..081db1a85b8a 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -22,6 +22,7 @@ #define QPNP_TM_REG_TYPE 0x04 #define QPNP_TM_REG_SUBTYPE 0x05 #define QPNP_TM_REG_STATUS 0x08 +#define QPNP_TM_REG_IRQ_STATUS 0x10 #define QPNP_TM_REG_SHUTDOWN_CTRL1 0x40 #define QPNP_TM_REG_ALARM_CTRL 0x46 @@ -29,14 +30,20 @@ #define QPNP_TM_REG_TEMP_DAC_STG1 0x47 #define QPNP_TM_REG_TEMP_DAC_STG2 0x48 #define QPNP_TM_REG_TEMP_DAC_STG3 0x49 +#define QPNP_TM_REG_LITE_TEMP_CFG1 0x50 +#define QPNP_TM_REG_LITE_TEMP_CFG2 0x51 #define QPNP_TM_TYPE 0x09 #define QPNP_TM_SUBTYPE_GEN1 0x08 #define QPNP_TM_SUBTYPE_GEN2 0x09 +#define QPNP_TM_SUBTYPE_LITE 0xC0 #define STATUS_GEN1_STAGE_MASK GENMASK(1, 0) #define STATUS_GEN2_STATE_MASK GENMASK(6, 4) +/* IRQ status only needed for TEMP_ALARM_LITE */ +#define IRQ_STATUS_MASK BIT(0) + #define SHUTDOWN_CTRL1_OVERRIDE_S2 BIT(6) #define SHUTDOWN_CTRL1_THRESHOLD_MASK GENMASK(1, 0) @@ -44,6 +51,8 @@ #define ALARM_CTRL_FORCE_ENABLE BIT(7) +#define LITE_TEMP_CFG_THRESHOLD_MASK GENMASK(3, 2) + #define THRESH_COUNT 4 #define STAGE_COUNT 3 @@ -88,6 +97,19 @@ static const long temp_dac_max[STAGE_COUNT] = { 119375, 159375, 159375 }; +/* + * TEMP_ALARM_LITE has two stages: warning and shutdown with independently + * configured threshold temperatures. + */ + +static const long temp_lite_warning_map[THRESH_COUNT] = { + 115000, 125000, 135000, 145000 +}; + +static const long temp_lite_shutdown_map[THRESH_COUNT] = { + 135000, 145000, 160000, 175000 +}; + /* Temperature in Milli Celsius reported during stage 0 if no ADC is present */ #define DEFAULT_TEMP 37000 @@ -197,6 +219,24 @@ static int qpnp_tm_gen2_get_temp_stage(struct qpnp_tm_chip *chip) return alarm_state_map[ret]; } +/** + * qpnp_tm_lite_get_temp_stage() - return over-temperature stage + * @chip: Pointer to the qpnp_tm chip + * + * Return: alarm interrupt state on success, or errno on failure. + */ +static int qpnp_tm_lite_get_temp_stage(struct qpnp_tm_chip *chip) +{ + u8 reg = 0; + int ret; + + ret = qpnp_tm_read(chip, QPNP_TM_REG_IRQ_STATUS, ®); + if (ret < 0) + return ret; + + return reg & IRQ_STATUS_MASK; +} + /* * This function updates the internal temp value based on the * current thermal stage and threshold as well as the previous stage @@ -376,6 +416,96 @@ static const struct thermal_zone_device_ops qpnp_tm_gen2_rev2_sensor_ops = { .set_trip_temp = qpnp_tm_gen2_rev2_set_trip_temp, }; +static int qpnp_tm_lite_set_temp_thresh(struct qpnp_tm_chip *chip, int trip, int temp) +{ + int ret, temp_cfg, i; + const long *temp_map; + u16 addr; + u8 reg, thresh; + + if (trip < 0 || trip >= STAGE_COUNT) { + dev_err(chip->dev, "invalid TEMP_LITE trip = %d\n", trip); + return -EINVAL; + } + + switch (trip) { + case 0: + temp_map = temp_lite_warning_map; + addr = QPNP_TM_REG_LITE_TEMP_CFG1; + break; + case 1: + /* + * The second trip point is purely in software to facilitate + * a controlled shutdown after the warning threshold is crossed + * but before the automatic hardware shutdown threshold is + * crossed. + */ + return 0; + case 2: + temp_map = temp_lite_shutdown_map; + addr = QPNP_TM_REG_LITE_TEMP_CFG2; + break; + default: + return 0; + } + + if (temp < temp_map[THRESH_MIN] || temp > temp_map[THRESH_MAX]) { + dev_err(chip->dev, "invalid TEMP_LITE temp = %d\n", temp); + return -EINVAL; + } + + thresh = 0; + temp_cfg = temp_map[thresh]; + for (i = THRESH_MAX; i >= THRESH_MIN; i--) { + if (temp >= temp_map[i]) { + thresh = i; + temp_cfg = temp_map[i]; + break; + } + } + + if (temp_cfg == chip->temp_thresh_map[trip]) + return 0; + + ret = qpnp_tm_read(chip, addr, ®); + if (ret < 0) { + dev_err(chip->dev, "LITE_TEMP_CFG read failed, ret=%d\n", ret); + return ret; + } + + reg &= ~LITE_TEMP_CFG_THRESHOLD_MASK; + reg |= FIELD_PREP(LITE_TEMP_CFG_THRESHOLD_MASK, thresh); + + ret = qpnp_tm_write(chip, addr, reg); + if (ret < 0) { + dev_err(chip->dev, "LITE_TEMP_CFG write failed, ret=%d\n", ret); + return ret; + } + + chip->temp_thresh_map[trip] = temp_cfg; + + return 0; +} + +static int qpnp_tm_lite_set_trip_temp(struct thermal_zone_device *tz, + const struct thermal_trip *trip, int temp) +{ + unsigned int trip_index = THERMAL_TRIP_PRIV_TO_INT(trip->priv); + struct qpnp_tm_chip *chip = thermal_zone_device_priv(tz); + int ret; + + mutex_lock(&chip->lock); + ret = qpnp_tm_lite_set_temp_thresh(chip, trip_index, temp); + mutex_unlock(&chip->lock); + + return ret; +} + +static const struct thermal_zone_device_ops qpnp_tm_lite_sensor_ops = { + .get_temp = qpnp_tm_get_temp, + .set_trip_temp = qpnp_tm_lite_set_trip_temp, +}; + static irqreturn_t qpnp_tm_isr(int irq, void *data) { struct qpnp_tm_chip *chip = data; @@ -452,6 +582,68 @@ static int qpnp_tm_gen2_rev2_init(struct qpnp_tm_chip *chip) return 0; } +/* Configure TEMP_LITE registers based on DT thermal_zone trips */ +static int qpnp_tm_lite_configure_trip_temps_cb(struct thermal_trip *trip, void *data) +{ + struct qpnp_tm_chip *chip = data; + int ret; + + trip->priv = THERMAL_INT_TO_TRIP_PRIV(chip->ntrips); + ret = qpnp_tm_lite_set_temp_thresh(chip, chip->ntrips, trip->temperature); + chip->ntrips++; + + return ret; +} + +static int qpnp_tm_lite_configure_trip_temps(struct qpnp_tm_chip *chip) +{ + int ret; + + ret = thermal_zone_for_each_trip(chip->tz_dev, qpnp_tm_lite_configure_trip_temps_cb, chip); + if (ret < 0) + return ret; + + /* Verify that trips are strictly increasing. */ + if (chip->temp_thresh_map[2] <= chip->temp_thresh_map[0]) { + dev_err(chip->dev, "Threshold 2=%ld <= threshold 0=%ld\n", + chip->temp_thresh_map[2], chip->temp_thresh_map[0]); + return -EINVAL; + } + + return 0; +} + +/* Read the hardware default TEMP_LITE stage threshold temperatures */ +static int qpnp_tm_lite_init(struct qpnp_tm_chip *chip) +{ + int ret, thresh; + u8 reg = 0; + + /* + * Store the warning trip temp in temp_thresh_map[0] and the shutdown trip + * temp in temp_thresh_map[2]. The second trip point is purely in software + * to facilitate a controlled shutdown after the warning threshold is + * crossed but before the automatic hardware shutdown threshold is + * crossed. Thus, there is no register to read for the second trip + * point. + */ + ret = qpnp_tm_read(chip, QPNP_TM_REG_LITE_TEMP_CFG1, ®); + if (ret < 0) + return ret; + + thresh = FIELD_GET(LITE_TEMP_CFG_THRESHOLD_MASK, reg); + chip->temp_thresh_map[0] = temp_lite_warning_map[thresh]; + + ret = qpnp_tm_read(chip, QPNP_TM_REG_LITE_TEMP_CFG2, ®); + if (ret < 0) + return ret; + + thresh = FIELD_GET(LITE_TEMP_CFG_THRESHOLD_MASK, reg); + chip->temp_thresh_map[2] = temp_lite_shutdown_map[thresh]; + + return 0; +} + static const struct spmi_temp_alarm_data spmi_temp_alarm_data = { .ops = &qpnp_tm_sensor_ops, .temp_map = &temp_map_gen1, @@ -480,6 +672,13 @@ static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_rev2_data = { .get_temp_stage = qpnp_tm_gen2_get_temp_stage, }; +static const struct spmi_temp_alarm_data spmi_temp_alarm_lite_data = { + .ops = &qpnp_tm_lite_sensor_ops, + .setup = qpnp_tm_lite_init, + .configure_trip_temps = qpnp_tm_lite_configure_trip_temps, + .get_temp_stage = qpnp_tm_lite_get_temp_stage, +}; + /* * This function initializes the internal temp value based on only the * current thermal stage and threshold. Setup threshold control and @@ -605,7 +804,8 @@ static int qpnp_tm_probe(struct platform_device *pdev) } if (type != QPNP_TM_TYPE || (subtype != QPNP_TM_SUBTYPE_GEN1 - && subtype != QPNP_TM_SUBTYPE_GEN2)) { + && subtype != QPNP_TM_SUBTYPE_GEN2 + && subtype != QPNP_TM_SUBTYPE_LITE)) { dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n", type, subtype); return -ENODEV; @@ -621,6 +821,8 @@ static int qpnp_tm_probe(struct platform_device *pdev) chip->data = &spmi_temp_alarm_gen2_rev1_data; else if (subtype == QPNP_TM_SUBTYPE_GEN2) chip->data = &spmi_temp_alarm_gen2_data; + else if (subtype == QPNP_TM_SUBTYPE_LITE) + chip->data = &spmi_temp_alarm_lite_data; else return -ENODEV;