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Fri, 21 Feb 2025 05:07:10 -0800 (PST) From: Abel Vesa Date: Fri, 21 Feb 2025 15:07:03 +0200 Subject: [PATCH v2] arm64: dts: qcom: x1e80100: Add crypto engine Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250221-x1e80100-crypto-v2-1-413ecf68dcd7@linaro.org> X-B4-Tracking: v=1; b=H4sIAHZ6uGcC/3WNzQqDMBCEX0X23JRsVKo99T2Kh5AfXSiJbCQok ndv6r3Hb5j55oTkmFyCZ3MCu0yJYqigbg2YRYfZCbKVQUnVS4Wt2NENEqUUho91iwIH87DYGdv 1I9TVys7TfhnfU+WF0hb5uA4y/tL/rowChR9b7a3takm/PhQ0x3vkGaZSyhcHU+fNrwAAAA== X-Change-ID: 20250213-x1e80100-crypto-18c7d14cd459 To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Johan Hovold , Stephan Gerhold , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.15-dev-dedf8 X-Developer-Signature: v=1; a=openpgp-sha256; l=2208; i=abel.vesa@linaro.org; h=from:subject:message-id; bh=Wuq8PZZqTZmX+Wwqcw5TIBdEiOB/HRphCwfmFoMd2sA=; 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Describe the crypto engine and its BAM. Signed-off-by: Abel Vesa --- The dt-binding schema update for the x1e80100 compatible is here (already picked up): https://lore.kernel.org/all/20250213-dt-bindings-qcom-qce-x1e80100-v1-1-d17ef73a1c12@linaro.org/ --- Changes in v2: - Added EE and channels numbers in BAM node, like Stephan suggested. - Added v1.7.4 compatible as well. - Link to v1: https://lore.kernel.org/r/20250213-x1e80100-crypto-v1-1-f93afdd4025a@linaro.org --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) --- base-commit: d4b0fd87ff0d4338b259dc79b2b3c6f7e70e8afa change-id: 20250213-x1e80100-crypto-18c7d14cd459 Best regards, diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 9d38436763432892ceef95daf0335d4cf446357c..71d5f5eed4511030a51fb12e453f603d294080cc 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3708,6 +3708,38 @@ pcie4_phy: phy@1c0e000 { status = "disabled"; }; + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; + reg = <0 0x01dc4000 0 0x28000>; + + interrupts = ; + + #dma-cells = <1>; + + iommus = <&apps_smmu 0x480 0>, + <&apps_smmu 0x481 0>; + + qcom,ee = <0>; + qcom,num-ees = <7>; + num-channels = <30>; + qcom,controlled-remotely; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,x1e80100-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0 0x01dfa000 0 0x6000>; + + interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "memory"; + + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + + iommus = <&apps_smmu 0x480 0>, + <&apps_smmu 0x481 0>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0 0x01f40000 0 0x20000>;