diff mbox series

[v2,3/8] dt-bindings: phy: add samsung,exynos2200-usbcon-phy schema file

Message ID 20250223122227.725233-4-ivo.ivanov.ivanov1@gmail.com
State New
Headers show
Series [v2,1/8] dt-bindings: phy: rename qcom,snps-eusb2-phy binding to snps,eusb2-phy | expand

Commit Message

Ivaylo Ivanov Feb. 23, 2025, 12:22 p.m. UTC 
The Exynos2200 SoC has a USB controller PHY, which acts as an
intermediary between a USB controller (typically DWC3) and other PHYs
(UTMI, PIPE3). Add a dt-binding schema for it.

Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
---
 .../phy/samsung,exynos2200-usbcon-phy.yaml    | 76 +++++++++++++++++++
 1 file changed, 76 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/samsung,exynos2200-usbcon-phy.yaml
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/phy/samsung,exynos2200-usbcon-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,exynos2200-usbcon-phy.yaml
new file mode 100644
index 000000000..7d879ec8b
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/samsung,exynos2200-usbcon-phy.yaml
@@ -0,0 +1,76 @@ 
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/samsung,exynos2200-usbcon-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Exynos2200 USB controller PHY
+
+maintainers:
+  - Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
+
+description:
+  Exynos2200 USB controller PHY is an intermediary between a USB controller
+  (typically DWC3) and other PHYs (UTMI, PIPE3).
+
+properties:
+  compatible:
+    enum:
+      - samsung,exynos2200-usbcon-phy
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: bus clock
+
+  clock-names:
+    items:
+      - const: bus
+
+  "#phy-cells":
+    const: 0
+
+  phys:
+    maxItems: 1
+    description:
+      Phandle to eUSB2 PHY
+
+  samsung,pmu-syscon:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+    items:
+      minItems: 1
+      items:
+        - description: phandle for PMU system controller interface, used to
+                       control PMU registers bits for USBCON PHY
+        - description: offset of the pmu control register
+    description:
+      Should be phandle/offset pair. The phandle to System Register syscon node
+      and the offset for USBCON PHY.
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - "#phy-cells"
+  - phys
+  - samsung,pmu-syscon
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/samsung,exynos2200-cmu.h>
+
+    usb_con_phy: phy@10aa0000 {
+        compatible = "samsung,exynos2200-usbcon-phy";
+        reg = <0x10aa0000 0x10000>;
+        clocks = <&cmu_hsi0 CLK_MOUT_HSI0_NOC>;
+        clock-names = "bus";
+        #phy-cells = <0>;
+        phys = <&usb_hs_phy>;
+        samsung,pmu-syscon = <&pmu_system_controller 0x72c>;
+    };