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Thu, 27 Feb 2025 20:14:22 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-549441262b9sm361101e87.0.2025.02.27.20.14.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Feb 2025 20:14:21 -0800 (PST) From: Dmitry Baryshkov Date: Fri, 28 Feb 2025 06:14:09 +0200 Subject: [PATCH v2 5/8] drm/msm/dpu: don't select single flush for active CTL blocks Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250228-dpu-active-ctl-v2-5-9a9df2ee5193@linaro.org> References: <20250228-dpu-active-ctl-v2-0-9a9df2ee5193@linaro.org> In-Reply-To: <20250228-dpu-active-ctl-v2-0-9a9df2ee5193@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1072; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=Mj6W/g1cQTXrPDSCV2G/UAnCYQZDcnBUJoxZDb1VnZ4=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnwTgP4KRcHBqD2Y7auegS7rtZ5I4melMFiEZdK 0WuqCAAgLOJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ8E4DwAKCRCLPIo+Aiko 1XA7B/4lyHDEWi+MrQa5obFMN7alj9kvr0s/v5T0MSenczs9W5rOlcwWgZwtTlYOZ0DwtObtB8P 1X2H6gJTY2PPKPmSET/iTt/PH/cf4ey3p1+ho8iogaBa9aykS5QeNavZpoRvwhTYv0BbdB2IinW IBtEFNuQFymgDrk7J5xvTIRfu7ncagUaFRgx/abgr2CDHIYmqI6tx4gmx+bIGmIliknpmSVh3lE TCqBeu4QnT5pa1V0XSZYs0uBErCBw1ukukGyaffORJx51BxxAqyO7G8K934LDptaVpm43kF8wZq lMZRTp6stKw5JrcxfjzZrZmv9aCoJ7AQw7s4Udj2IYgbVShB X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A In case of ACTIVE CTLs, a single CTL is being used for flushing all INTF blocks. Don't skip programming the CTL on those targets. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 232055473ba55998b79dd2e8c752c129bbffbff4..8a618841e3ea89acfe4a42d48319a6c54a1b3495 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -374,7 +374,8 @@ static void dpu_encoder_phys_vid_underrun_irq(void *arg) static bool dpu_encoder_phys_vid_needs_single_flush( struct dpu_encoder_phys *phys_enc) { - return phys_enc->split_role != ENC_ROLE_SOLO; + return !(phys_enc->hw_ctl->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) && + phys_enc->split_role != ENC_ROLE_SOLO; } static void dpu_encoder_phys_vid_atomic_mode_set(