From patchwork Thu Mar 13 08:06:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 873205 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 412C9260390; Thu, 13 Mar 2025 08:06:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741853208; cv=none; b=q7FY222U0MHOiMW/4J2wtf14f2c8CtDY9OfOmG3v8oRG8xHIgbStoy8xB0C7Flai/3lejgFQ55kJRkVX7+Ar/fVKlmdvp2fN3BuggjKAJ0eU5ZVjP3N+oMYGT73/Y/jj0Ku6F53m0rNsn6qagFSZvI+djRVUnyAak6rK2qgilx8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741853208; c=relaxed/simple; bh=bR9JTHQ6TPxSLmWg0pU6f/wQvuPkKUdbi2FXj8T2sUk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=f0CgUKt4Flh2P4tgC42BlqYKUk6vxKuwQeiIdW6HzPPdJS9IyHJan0I+gueGdLDpS8c/EqPJ1vYK+Dzcy0uNQiWb+EfN20eGbj0R48je1yliA89PNW8JRA8MoJw58JKn3mYWRpN+Sm6QLEL0/3IVex8yyNH2eN5eGLMFBqm8uY0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=KuB0zno4; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="KuB0zno4" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 52D7RUpd022536; Thu, 13 Mar 2025 08:06:37 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= U3d4rtPbAvYi3k2CRRFl+IrbVJFOaPAb+Wt2WZKaqoc=; b=KuB0zno4r9dwQ0KZ EQQWQgtxhNpwnZFC41uRcj/76XFzhcLNDW+I/sCh31MQUsxY+k3LzP1VEdBnwmfD 6xrArfEej5WkVm0NSn87Me2b9YH+5U/VRMZp6NAz9Ez6mj1JeF0FjFY/jIeTJQPQ /JhtWfMnRxmI+2JxoNHHel0cGECyltyrJvMNA3dMccHayIPM+Xu80CO9x235MVZu BTDABAw/5UtERlqLu+2fPMRgY46JkPowFrlljpgu15vsrD7y7j2kWNyhtY7b+8fs Anc1+LquBMeoGMUzxyc0wWB7AMFHiRztZn3WneL6DuCZm+u0hOAe0I9u7E0iOsN6 MCWwrA== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 45bu07g3bv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Mar 2025 08:06:36 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 52D86Z4B009459 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Mar 2025 08:06:35 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 13 Mar 2025 01:06:30 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , CC: Praveenkumar I , Konrad Dybcio , Varadarajan Narayanan Subject: [PATCH v13 4/4] arm64: dts: qcom: ipq5332-rdp441: Enable PCIe phys and controllers Date: Thu, 13 Mar 2025 13:36:00 +0530 Message-ID: <20250313080600.1719505-5-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250313080600.1719505-1-quic_varada@quicinc.com> References: <20250313080600.1719505-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: k0xUxxI_b8SNfpMhRNq8wLEiqp_hz12p X-Authority-Analysis: v=2.4 cv=V+F90fni c=1 sm=1 tr=0 ts=67d2920c cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=A71FK_BBuJjt25o-iSMA:9 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: k0xUxxI_b8SNfpMhRNq8wLEiqp_hz12p X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-13_04,2025-03-11_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxlogscore=838 impostorscore=0 spamscore=0 priorityscore=1501 phishscore=0 mlxscore=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 adultscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503130063 From: Praveenkumar I Enable the PCIe controller and PHY nodes for RDP 441. Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Praveenkumar I Signed-off-by: Varadarajan Narayanan --- arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 76 +++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts index 846413817e9a..79ec77cfe552 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts @@ -32,6 +32,34 @@ &sdhc { status = "okay"; }; +&pcie0 { + pinctrl-0 = <&pcie0_default>; + pinctrl-names = "default"; + + perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&pcie0_phy { + status = "okay"; +}; + +&pcie1 { + pinctrl-0 = <&pcie1_default>; + pinctrl-names = "default"; + + perst-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; +}; + &tlmm { i2c_1_pins: i2c-1-state { pins = "gpio29", "gpio30"; @@ -40,6 +68,54 @@ i2c_1_pins: i2c-1-state { bias-pull-up; }; + pcie0_default: pcie0-default-state { + clkreq-n-pins { + pins = "gpio37"; + function = "pcie0_clk"; + drive-strength = <8>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio38"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + output-low; + }; + + wake-n-pins { + pins = "gpio39"; + function = "pcie0_wake"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + pcie1_default: pcie1-default-state { + clkreq-n-pins { + pins = "gpio46"; + function = "pcie1_clk"; + drive-strength = <8>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio47"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + output-low; + }; + + wake-n-pins { + pins = "gpio48"; + function = "pcie1_wake"; + drive-strength = <8>; + bias-pull-up; + }; + }; + sdc_default_state: sdc-default-state { clk-pins { pins = "gpio13";