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Thu, 13 Mar 2025 13:10:19 GMT Received: from hu-kaushalk-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 13 Mar 2025 06:10:14 -0700 From: Kaushal Kumar To: , , , , , , , , , , CC: , , , , , Kaushal Kumar Subject: [PATCH 4/6] ARM: dts: qcom: sdx75: Add QPIC NAND support Date: Thu, 13 Mar 2025 18:39:16 +0530 Message-ID: <20250313130918.4238-5-quic_kaushalk@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250313130918.4238-1-quic_kaushalk@quicinc.com> References: <20250313130918.4238-1-quic_kaushalk@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: llwNpGjssWlrA_wVgC-nalL_RIwbOYRa X-Authority-Analysis: v=2.4 cv=Q4XS452a c=1 sm=1 tr=0 ts=67d2d93c cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=aSCKG8iKwtCOJjoOL2oA:9 a=fXBJl3N8H64iLEq10rD0:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: llwNpGjssWlrA_wVgC-nalL_RIwbOYRa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-13_06,2025-03-11_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=900 adultscore=0 lowpriorityscore=0 mlxscore=0 clxscore=1011 phishscore=0 malwarescore=0 spamscore=0 impostorscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503130103 Add devicetree node to enable support for QPIC NAND controller on Qualcomm SDX75 platform. Since there is no "aon" clock in SDX75, a dummy clock is provided. Signed-off-by: Kaushal Kumar --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index e3a0ee661c4a..9c43b14a0594 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -37,6 +37,12 @@ clock-frequency = <32764>; #clock-cells = <0>; }; + + nand_clk_dummy: nand-clk-dummy { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; }; cpus { @@ -894,6 +900,24 @@ status = "disabled"; }; + qpic_nand: nand-controller@1cc8000 { + compatible = "qcom,sdx75-nand", "qcom,sdx55-nand"; + reg = <0x0 0x01cc8000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&rpmhcc RPMH_QPIC_CLK>, + <&nand_clk_dummy>; + clock-names = "core", "aon"; + + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", "rx", "cmd"; + iommus = <&apps_smmu 0x100 0x3>; + dma-coherent; + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>;