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[2001:1c06:2302:5600:7555:cca3:bbc4:648b]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3146aeadbsm284246966b.29.2025.03.14.16.36.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Mar 2025 16:36:03 -0700 (PDT) From: Bryan O'Donoghue Date: Fri, 14 Mar 2025 23:35:58 +0000 Subject: [PATCH v2 5/7] media: qcom: camss: Add support for 3ph CSIPHY write settle delay Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250314-b4-media-comitters-next-25-03-13-x1e80100-camss-driver-v2-5-d163d66fcc0d@linaro.org> References: <20250314-b4-media-comitters-next-25-03-13-x1e80100-camss-driver-v2-0-d163d66fcc0d@linaro.org> In-Reply-To: <20250314-b4-media-comitters-next-25-03-13-x1e80100-camss-driver-v2-0-d163d66fcc0d@linaro.org> To: Robert Foss , Todor Tomov , Mauro Carvalho Chehab Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue , Vladimir Zapolskiy X-Mailer: b4 0.14.2 Currently we have an s32 value called delay which has been inherited from the CamX code for PHY init. This unused value relates to a post-write delay latching time. In the silicon test-bench which provides the basis for the CamX code the write settle times are specified in nanoseconds. In the upstream kernel we currently take no notice of the delay value and use all zero in any case. Nanosecond granularity timing from the perspective of the kernel is total overkill, however for some PHY init sequences introduction of a settle delay has a use. Add support to the 3ph init sequence for microsecond level delay. A readback of written data would probably accomplish the same thing but, since the PHY init sequences in the wild provide a delay value - we can just add support here for that delay and consume the values given. Generally these delays are probably not necessary but, they do speak to a theoretical delay that silicon test-benches utilise and therefore are worthwhile to replicate if the given PHY init sequence has the data. Reviewed-by: Vladimir Zapolskiy Signed-off-by: Bryan O'Donoghue --- drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index a6cc957b986e16add9da516c2fcb3201f3a65f35..b44939686e4bbf400f145368d3ba015b56bfb187 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -59,7 +59,7 @@ struct csiphy_lane_regs { s32 reg_addr; s32 reg_data; - s32 delay; + u32 delay_us; u32 csiphy_param_type; }; @@ -600,6 +600,8 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy, break; } writel_relaxed(val, csiphy->base + r->reg_addr); + if (r->delay_us) + udelay(r->delay_us); } }