| Message ID | 20250509-a623-gpu-support-v4-2-d4da14600501@quicinc.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Support for Adreno 623 GPU | expand |
On 5/9/25 9:21 AM, Akhil P Oommen wrote: > From: Jie Zhang <quic_jiezh@quicinc.com> > > Add gpu and gmu nodes for qcs8300 chipset. > > Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com> > Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qcs8300.dtsi | 91 +++++++++++++++++++++++++++++++++++ > 1 file changed, 91 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi > index 40771b062e8d7010dd93d7cc7b3db73cfa16bfdb..1dbccb9a0c75366aa6986b6adb4feb6164ee8845 100644 > --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi > @@ -2660,6 +2660,97 @@ serdes0: phy@8909000 { > status = "disabled"; > }; > > + gpu: gpu@3d00000 { > + compatible = "qcom,adreno-623.0", "qcom,adreno"; > + reg = <0x0 0x03d00000 0x0 0x40000>, I haven't noticed it up until now.. this should be moved up in the file to sort the nodes by unit address (the serdes node above is 0x089.., gpu is 0x03d..) Otherwise, please check if there are freq fuses on this platform, if not, feel free to add: Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Konrad
On 5/13/2025 2:18 AM, Konrad Dybcio wrote: > On 5/9/25 9:21 AM, Akhil P Oommen wrote: >> From: Jie Zhang <quic_jiezh@quicinc.com> >> >> Add gpu and gmu nodes for qcs8300 chipset. >> >> Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com> >> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> >> --- > > >> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 91 +++++++++++++++++++++++++++++++++++ >> 1 file changed, 91 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi >> index 40771b062e8d7010dd93d7cc7b3db73cfa16bfdb..1dbccb9a0c75366aa6986b6adb4feb6164ee8845 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi >> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi >> @@ -2660,6 +2660,97 @@ serdes0: phy@8909000 { >> status = "disabled"; >> }; >> >> + gpu: gpu@3d00000 { >> + compatible = "qcom,adreno-623.0", "qcom,adreno"; >> + reg = <0x0 0x03d00000 0x0 0x40000>, > > I haven't noticed it up until now.. this should be moved up in the file > to sort the nodes by unit address (the serdes node above is 0x089.., gpu > is 0x03d..) Looks like GPUCC block got misplaced too. Will fix. > > Otherwise, please check if there are freq fuses on this platform, if not, > feel free to add: > > Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Thanks. We have the SKU related data available. We will add those too in the next revision. -Akhil > > Konrad >
diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 40771b062e8d7010dd93d7cc7b3db73cfa16bfdb..1dbccb9a0c75366aa6986b6adb4feb6164ee8845 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -2660,6 +2660,97 @@ serdes0: phy@8909000 { status = "disabled"; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-623.0", "qcom,adreno"; + reg = <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&adreno_smmu 0 0xc00>, + <&adreno_smmu 1 0xc00>; + operating-points-v2 = <&gpu_opp_table>; + qcom,gmu = <&gmu>; + interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "gfx-mem"; + #cooling-cells = <2>; + + status = "disabled"; + + gpu_zap_shader: zap-shader { + memory-region = <&gpu_microcode_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-877000000 { + opp-hz = /bits/ 64 <877000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + opp-peak-kBps = <12484375>; + }; + + opp-780000000 { + opp-hz = /bits/ 64 <780000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + opp-peak-kBps = <10687500>; + }; + + opp-599000000 { + opp-hz = /bits/ 64 <599000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + opp-peak-kBps = <8171875>; + }; + + opp-479000000 { + opp-hz = /bits/ 64 <479000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + opp-peak-kBps = <5285156>; + }; + }; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-623.0", "qcom,adreno-gmu"; + reg = <0x0 0x03d6a000 0x0 0x34000>, + <0x0 0x03de0000 0x0 0x10000>, + <0x0 0x0b290000 0x0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>; + clock-names = "gmu", + "cxo", + "axi", + "memnoc", + "ahb", + "hub"; + power-domains = <&gpucc GPU_CC_CX_GDSC>, + <&gpucc GPU_CC_GX_GDSC>; + power-domain-names = "cx", + "gx"; + iommus = <&adreno_smmu 5 0xc00>; + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,qcs8300-gpucc"; reg = <0x0 0x03d90000 0x0 0xa000>;