From patchwork Tue Jun 10 08:37:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Moussalem via B4 Relay X-Patchwork-Id: 895304 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F06441DD9D3; Tue, 10 Jun 2025 08:38:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749544687; cv=none; b=oaELl71hjfVUVFhrorR5904o0qUx9sosO5iyG9IR8zv9RWKp7u2fZrEstSK5QILH9/ev4ONxJNiiaCwln5J8aDxlgHVr4hHtrfnCDVTcROBi+Y9cT25udmgS556/LqA8oJLP0RKiEhbffMDLE8BTHHrZbeEs229bPb889w4isE8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749544687; c=relaxed/simple; bh=8Y2htiPy5meWxzHXQzhyzo1AQtbeIgcyev3Yn6FKh6Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dei5MTZijvsmFLI9sD0tcviSBgVcy/dLI91tVID0l0B5A3CvTxFaan0f1S0K9uemjjuEmO9es8TMq5XFFRL5yphHvNwJQz8LMNyTWtID5w+mODNhDPX6frqxglpB0ekJVMLn/pc8a+uthQYWpOfXM+K8snswMZEe2qBLcpmIJfo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ePZhZU14; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ePZhZU14" Received: by smtp.kernel.org (Postfix) with ESMTPS id 9364BC4CEF2; Tue, 10 Jun 2025 08:38:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1749544686; bh=8Y2htiPy5meWxzHXQzhyzo1AQtbeIgcyev3Yn6FKh6Q=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ePZhZU14Sp+y0japK5Gby46W1qZDL32cvhjiA3hAfq8/KujcPEP0TMMoIAyrFhLWT SmBq5zKXA1Wn0+J4iaAULcA3HXfHHxOApGeRMVOAkRRke4EkbZyrdoS1/CsZRzqhA2 pKnhNvzjpjIQ45PQqy8Bb48AEJruxmrhbFq1RDrVCA6IQv7fiwqCLJdeV7DW8jRmBg ELiLu9llNyTCMxJYAvxqvZ9vqWISpUXpZI9X1XmOmQ3qTWc0IETy/0y0omPQGkde20 nY2X96+2qrfpqC1paMt9cC0QqtbaAOPeiaCtRUeGdcRs6a918XRnZGSq/kEBXk0k2u TjQZysrRUcO8w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82A05C61DB2; Tue, 10 Jun 2025 08:38:06 +0000 (UTC) From: George Moussalem via B4 Relay Date: Tue, 10 Jun 2025 12:37:55 +0400 Subject: [PATCH v5 1/5] clk: qcom: gcc-ipq5018: fix GE PHY reset Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250610-ipq5018-ge-phy-v5-1-daa9694bdbd1@outlook.com> References: <20250610-ipq5018-ge-phy-v5-0-daa9694bdbd1@outlook.com> In-Reply-To: <20250610-ipq5018-ge-phy-v5-0-daa9694bdbd1@outlook.com> To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, George Moussalem , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1749544683; l=1220; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=y65n0Od6u+x9wP3HKotpTyPdgu84le/dyFb7G8W0t/E=; b=FwKHoMxaPysoeaqp1bvm0yyBuOQ2kyrcMP02yVlcHy+ILSyZMWinN2ckZoTJsWATaat4x5sMI /NV40gSj9rjC18x8QfHsmFINGdbBCekMd4Kg7r6tE8J0veib/BBLsda X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The MISC reset is supposed to trigger a resets across the MDC, DSP, and RX & TX clocks of the IPQ5018 internal GE PHY. So let's set the bitmask of the reset definition accordingly in the GCC as per the downstream driver. Link: https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/00743c3e82fa87cba4460e7a2ba32f473a9ce932 Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem --- drivers/clk/qcom/gcc-ipq5018.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c index 70f5dcb96700f55da1fb19fc893d22350a7e63bf..6eb86c034fda18c38dcd9726f0903841252381da 100644 --- a/drivers/clk/qcom/gcc-ipq5018.c +++ b/drivers/clk/qcom/gcc-ipq5018.c @@ -3660,7 +3660,7 @@ static const struct qcom_reset_map gcc_ipq5018_resets[] = { [GCC_WCSS_AXI_S_ARES] = { 0x59008, 6 }, [GCC_WCSS_Q6_BCR] = { 0x18004, 0 }, [GCC_WCSSAON_RESET] = { 0x59010, 0}, - [GCC_GEPHY_MISC_ARES] = { 0x56004, 0 }, + [GCC_GEPHY_MISC_ARES] = { 0x56004, .bitmask = GENMASK(3, 0) }, }; static const struct of_device_id gcc_ipq5018_match_table[] = {