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[88.112.131.206]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-553a7018069sm62808e87.157.2025.06.11.18.15.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jun 2025 18:15:53 -0700 (PDT) From: Vladimir Zapolskiy To: Krzysztof Kozlowski , Rob Herring , Bjorn Andersson , Konrad Dybcio , Bryan O'Donoghue Cc: Conor Dooley , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Neil Armstrong , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 08/10] dt-bindings: media: qcom: Add Qualcomm MIPI C-/D-PHY schema for CSIPHY IPs Date: Thu, 12 Jun 2025 04:15:29 +0300 Message-ID: <20250612011531.2923701-9-vladimir.zapolskiy@linaro.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250612011531.2923701-1-vladimir.zapolskiy@linaro.org> References: <20250612011531.2923701-1-vladimir.zapolskiy@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add dt-binding schema for Qualcomm CAMSS CSIPHY IP, which provides MIPI C-PHY/D-PHY interfaces on Qualcomm SoCs. Signed-off-by: Vladimir Zapolskiy --- RFC verion of the change: * https://lore.kernel.org/all/20250513143918.2572689-1-vladimir.zapolskiy@linaro.org/ Changes from RFC to v1: * moved from phy/qcom,csiphy.yaml to media/qcom,csiphy.yaml, * added 'clock-names' property, * removed SM8250 CSIPHY specifics, a generic binding is good enough for now, * the above implies a removal of SM8250 specific supplies. .../bindings/media/qcom,csiphy.yaml | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/qcom,csiphy.yaml diff --git a/Documentation/devicetree/bindings/media/qcom,csiphy.yaml b/Documentation/devicetree/bindings/media/qcom,csiphy.yaml new file mode 100644 index 000000000000..699824e7c44d --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,csiphy.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,csiphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm CSI PHY + +maintainers: + - Vladimir Zapolskiy + +description: + Qualcomm SoCs equipped with a number of MIPI CSI PHY IPs, which + supports D-PHY or C-PHY interfaces to camera sensors. + +properties: + compatible: + enum: + - qcom,csiphy + + reg: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: csiphy + - const: csiphy_timer + + interrupts: + maxItems: 1 + + "#phy-cells": + const: 0 + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + description: CAMSS CSIPHY input port + + patternProperties: + "^endpoint@[0-1]$": + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - data-lanes + + oneOf: + - required: + - endpoint + - required: + - endpoint@0 + +required: + - compatible + - reg + - clocks + - interrupts + - "#phy-cells" + +additionalProperties: true + +examples: + - | + #include + #include + #include + + phy@ac6e000 { + compatible = "qcom,csiphy"; + reg = <0x0ac6e000 0x1000>; + clocks = <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>; + clock-names = "csiphy", "csiphy_timer"; + interrupts = ; + #phy-cells = <0>; + + port { + csiphy_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&sensor_out>; + }; + }; + };