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Tue, 17 Jun 2025 19:08:34 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 17 Jun 2025 12:08:29 -0700 From: Jagadeesh Kona Date: Wed, 18 Jun 2025 00:37:26 +0530 Subject: [PATCH 1/2] dt-bindings: clock: qcom,sm8450-videocc: Add minItems property Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250618-sm8450-videocc-camcc-bindings-single-pd-fix-v1-1-02e83aeba280@quicinc.com> References: <20250618-sm8450-videocc-camcc-bindings-single-pd-fix-v1-0-02e83aeba280@quicinc.com> In-Reply-To: <20250618-sm8450-videocc-camcc-bindings-single-pd-fix-v1-0-02e83aeba280@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Vladimir Zapolskiy CC: Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , , Krzysztof Kozlowski , Jagadeesh Kona , kernel test robot X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjE3MDE1MyBTYWx0ZWRfX0680tJlJOLNn RfiNG4x4L+VTpX+2qywBIP+JtmcsHclq+ddqGSAYsDXBp5gNj2TCauXYVyhThsTsznX4sBl7fGh B/MQNEsZSW/ur09mtGBuN+BHn3e5Les+psfxr0eK0viA3mRtbuWklJWKs4MZG8hkHzfceX4iSBD URJBM9N+7zxMeSjXUW7grfTVFXNHZ+M4IUgM7GkasUaziXDg7BvX7gCaLb2sjhFy+wdUFk9M8WU ZbMcYh1k/lIC6ho3fNX/HrH/8oil4YliQwcPXO46ON9P2fFbpLp1UAbTcEPjgW9efRXkqg/OZHE FUnC4b2vuMclYlnLzSoa7cYc2nBtTKIp/XvP91vtY8bLSgA0DEWrBsNVyGm4R9PKMPySgy3I0tU T77QyNK9qaoePu5Dd/8dkyjhEia+a4cS8zLCoo2NcC0PGuXjsjqqyG8kpxnDzqYi7/ss3anK X-Proofpoint-GUID: 9Qrr70tdsoYYbqEJy8LdwJiOueiXlhxd X-Proofpoint-ORIG-GUID: 9Qrr70tdsoYYbqEJy8LdwJiOueiXlhxd X-Authority-Analysis: v=2.4 cv=FrIF/3rq c=1 sm=1 tr=0 ts=6851bd33 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=6IFa9wvqVegA:10 a=VwQbUJbxAAAA:8 a=QyXUC8HyAAAA:8 a=COk6AnOGAAAA:8 a=-4hpY4AvdCWQGMI6cJkA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-17_08,2025-06-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 mlxlogscore=955 bulkscore=0 impostorscore=0 malwarescore=0 phishscore=0 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506170153 Add minItems as 1 for power-domains and required-opps properties to allow this binding to be compatible with both single and multiple power domains. This fixes: arch/arm64/boot/dts/qcom/sm8450-hdk.dtb: clock-controller@aaf0000 (qcom,sm8450-videocc): power-domains: [[106, 6]] is too short arch/arm64/boot/dts/qcom/sm8450-hdk.dtb: clock-controller@aaf0000 (qcom,sm8450-videocc): required-opps: [[55]] is too short Fixes: 1a42f4d4bb92 ("dt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain") Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202506141133.AEQRFOWe-lkp@intel.com/ Closes: https://lore.kernel.org/oe-kbuild-all/202506151907.LcLf1RIB-lkp@intel.com/ Signed-off-by: Jagadeesh Kona --- Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index 0d99178332cb99d3f02f50605e19b9b26e3ec807..e9143887c1739c28d3cfc97e6678ab12231472a6 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -32,6 +32,7 @@ properties: - description: Video AHB clock from GCC power-domains: + minItems: 1 description: Power domains required for the clock controller to operate items: @@ -39,6 +40,7 @@ properties: - description: MXC power domain required-opps: + minItems: 1 description: OPP nodes that describe required performance points on power domains items: