| Message ID | 20241122132044.30024-1-quic_yrangana@quicinc.com |
|---|---|
| Headers | show |
| Series | Enable Inline crypto engine for QCS8300 | expand |
On 22/11/2024 14:20, Yuvaraj Ranganathan wrote: > Add an ICE node to qcs8300 SoC description and enable it by adding a > phandle to the UFS node. > > Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> This did not happen. Provide a proof (lore link). Best regards, Krzysztof
Hi Krzysztof, Same mistake is done for this patch series as well. I sincerely apologize for the inconvenience. I will remove the tag in the next patch series. Thanks, Yuvaraj. On 11/22/2024 8:25 PM, Krzysztof Kozlowski wrote: > On 22/11/2024 14:20, Yuvaraj Ranganathan wrote: >> Add an ICE node to qcs8300 SoC description and enable it by adding a >> phandle to the UFS node. >> >> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> > > This did not happen. Provide a proof (lore link). > > Best regards, > Krzysztof
Document and add device-tree node to enable Inline crypto engine for QCS8300 This series depends on below patch series: https://lore.kernel.org/all/20240925-qcs8300_initial_dtsi-v2-0-494c40fa2a42@quicinc.com/ - Reviewed Changes in v2: - extend UFS ICE to the full register range - Link to v1: https://lore.kernel.org/all/20241113043351.2889027-1-quic_yrangana@quicinc.com/ Signed-off-by: Yuvaraj Ranganathan <quic_yrangana@quicinc.com> --- Yuvaraj Ranganathan (2): dt-bindings: crypto: ice: document the qcs8300 inline crypto engine arm64: dts: qcom: qcs8300: enable the inline crypto engine .../bindings/crypto/qcom,inline-crypto-engine.yaml | 1 + arch/arm64/boot/dts/qcom/qcs8300.dtsi | 8 ++++++++ 2 files changed, 9 insertions(+)