From patchwork Thu Dec 12 04:16:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Md Sadre Alam X-Patchwork-Id: 849843 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 883931632F2; Thu, 12 Dec 2024 04:18:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733977089; cv=none; b=PZ0uueYZatca6gC6etCvLop1Rbl22FBYzNGatmtO8tI7kHLiy0q3ahc4oWXb2qXUe+kxBJMg1x1ydtNVf3TT2aczuXegmSsGaq1q5wc6vfxXRFaqvqWdT5oHXHhwuYeEuZFYcrE7zegwU55xQ9twUYFjQuS8Ocp3j437vbQyf/A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733977089; c=relaxed/simple; bh=4FpesxTI8tOH3zp2gSxBusHmUxtqqSkPfa1kfXduHDo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=P5GWu1qF7V7DrYPa0BO7urR+153E0nNDYU9G0Smckg4EE2vmvmx/frg6TcyqKZg01TlhnfC098jcUvMJDyW8gcnHyd8rBnOzs6BzRtTXl5brB33wMWKfjtK1EcHYOdJnhb2uTks6ISxvimwdQgNZUdMznYY8u12zwhcUfKAcsps= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=ABbh1Js/; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ABbh1Js/" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4BBHD3Xg029041; Thu, 12 Dec 2024 04:17:59 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= pgacSY7WI6i9IX/ZwASO2aCI/5fwyVKaX18gcY/m2Xc=; b=ABbh1Js/QGdh6GGr WX2/yPa3DIn7dTLN8Pe0iRZSZy0TuudoiPUXaPZ1KLjHHiCKoX4W2Ipm9DOceCv8 ftpDgP6LAv3K+D/Xl5vq8a07N1E81GF30QGQT3NL3izejK2qD+ba/ue/qk9m7Hr9 W3AqakG471Vl4yg0AwauNfhtxyutqrvGCRMbrNUYu9ay8iSCT2glkMLQHlEJvhiH 3bbJkPiO4DROLKI9RMrL/Edd/jb9RITpw7kgBYsCSEGyDNXBZO1w75g2OiDJ81fg a5x1y8pgs9bHMHIegZX+Zh/GtNU2swBHH84TnoJ2Z9iLNnjZokSM/gbL7ZCqFOEX LuLyxg== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 43fd4xspt4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Dec 2024 04:17:59 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BC4HwDA021655 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 12 Dec 2024 04:17:58 GMT Received: from hu-mdalam-blr.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 11 Dec 2024 20:17:53 -0800 From: Md Sadre Alam To: , , , , , , , , , , , CC: , , , Subject: [PATCH v5 12/12] crypto: qce - Add support for lock/unlock in aead Date: Thu, 12 Dec 2024 09:46:39 +0530 Message-ID: <20241212041639.4109039-13-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241212041639.4109039-1-quic_mdalam@quicinc.com> References: <20241212041639.4109039-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: tg7I3zflIy5owK1CYaIt_Pglbvszj0p_ X-Proofpoint-GUID: tg7I3zflIy5owK1CYaIt_Pglbvszj0p_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 mlxlogscore=999 phishscore=0 adultscore=0 suspectscore=0 spamscore=0 mlxscore=0 impostorscore=0 clxscore=1015 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412120028 Add support for lock/unlock on bam pipe in aead. If multiple EE's(Execution Environment) try to access the same crypto engine then before accessing the crypto engine EE's has to lock the bam pipe and then submit the request to crypto engine. Once request done then EE's has to unlock the bam pipe so that others EE's can access the crypto engine. Signed-off-by: Md Sadre Alam --- Change in [v5] * No change Change in [v4] * No change Change in [v3] * Move qce_bam_release_lock() after qca_dma_terminate_all() api Change in [v2] * Added qce_bam_acquire_lock() and qce_bam_release_lock() api for aead Change in [v1] * This patch was not included in [v1] drivers/crypto/qce/aead.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/crypto/qce/aead.c b/drivers/crypto/qce/aead.c index 7d811728f047..13fb7af69f54 100644 --- a/drivers/crypto/qce/aead.c +++ b/drivers/crypto/qce/aead.c @@ -63,6 +63,8 @@ static void qce_aead_done(void *data) sg_free_table(&rctx->dst_tbl); } + qce_bam_release_lock(qce); + error = qce_check_status(qce, &status); if (error < 0 && (error != -EBADMSG)) dev_err(qce->dev, "aead operation error (%x)\n", status); @@ -433,6 +435,8 @@ qce_aead_async_req_handle(struct crypto_async_request *async_req) else rctx->assoclen = req->assoclen; + qce_bam_acquire_lock(qce); + diff_dst = (req->src != req->dst) ? true : false; dir_src = diff_dst ? DMA_TO_DEVICE : DMA_BIDIRECTIONAL; dir_dst = diff_dst ? DMA_FROM_DEVICE : DMA_BIDIRECTIONAL;