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[209.132.180.67]) by mx.google.com with ESMTP id n8si794263plk.532.2017.10.13.08.57.53; Fri, 13 Oct 2017 08:57:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=eKn464sw; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750990AbdJMP5w (ORCPT + 6 others); Fri, 13 Oct 2017 11:57:52 -0400 Received: from mail-wm0-f45.google.com ([74.125.82.45]:52846 "EHLO mail-wm0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750964AbdJMP5w (ORCPT ); Fri, 13 Oct 2017 11:57:52 -0400 Received: by mail-wm0-f45.google.com with SMTP id k4so22709183wmc.1 for ; Fri, 13 Oct 2017 08:57:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=hsa1awGR9PQuum/d1iZCSh8KWsUDN7TvbRt4znOY5Fk=; b=eKn464swiqK1BN3yoIxO0KlYLQfWxpRXUvRNCj+9/XxvIHDdY0+Z/vYLCOaD2XtA8G K/iAqNrZfz9NrAn1lriRvIvK6gdoNQrrLtRpYVQFSGka0yFcumQDNbEqb1QeY6bVGdj2 VIwc1eh6uIa2XkZbYJr0OBSlGvMuPYU/apNSU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=hsa1awGR9PQuum/d1iZCSh8KWsUDN7TvbRt4znOY5Fk=; b=p6GfW+nmoAqEUlHqhX842xPNppgn5qD/mUr0vqxrEpINnNCZJEMysPCg9JMuLcdUpp JzrdxN7Sr9nOa311S8QXUMY2VT50AKg/xNj3H5/dTQWFwomAOk2cphCY2sREYHfnnUKs QY3W2GuaxLTZPZyetC8bxfE3gwFmacLRcE2n1W/apxpRJ4Y7teNU3RljL50VfFSfnobc K1AXTXIqLnCEFIYPzNgLKUOxe+q0gr7cirD95WPDChoUJOChf/RYvTnMg9Gri7m0Ylpe Eh+beqj1oqzrWMbjqMzo28H6/rl/+2SXRU/weMonR/vEZGmsjLJ3FDrFcxs2UMoyfnyS VQPg== X-Gm-Message-State: AMCzsaVgrQElmI1L3pdlDK63u/f7QZLYWSTPlLW3NAC+cr+BNG5c7RQU uexi+N3wWMK6TiTVoM7sbNovzA== X-Google-Smtp-Source: ABhQp+TGAbisNAEWJ+3l51/Ght062hesjqtzjDKnnDsTid8Iw4auXhwoVYWQbqBVrs38XYIAR4L87w== X-Received: by 10.28.22.66 with SMTP id 63mr1784553wmw.11.1507910271131; Fri, 13 Oct 2017 08:57:51 -0700 (PDT) Received: from localhost.localdomain ([154.146.29.151]) by smtp.gmail.com with ESMTPSA id l19sm1636046wre.26.2017.10.13.08.57.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 13 Oct 2017 08:57:50 -0700 (PDT) From: Ard Biesheuvel To: marc.zyngier@arm.com, robin.murphy@arm.com Cc: linux-arm-kernel@lists.infradead.org, daniel.thompson@Linaro.org, leif.lindholm@linaro.org, graeme.gregory@linaro.org, catalin.marinas@arm.com, will.deacon@arm.com, devicetree@vger.kernel.org, robh+dt@kernel.org, Ard Biesheuvel Subject: [PATCH v4 0/3] implement workaround for Socionext Synquacer pre-ITS Date: Fri, 13 Oct 2017 16:56:04 +0100 Message-Id: <20171013155607.5211-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org >From patch 3/3: The Socionext Synquacer SoC's implementation of GICv3 has a so-called 'pre-ITS', which maps 32-bit writes targeted at a separate window of size '4 << device_id_bits' onto writes to GITS_TRANSLATER with device ID taken from bits [device_id_bits + 1:2] of the window offset. Writes that target GITS_TRANSLATER directly are reported as originating from device ID #0. So add a workaround for this. Given that this breaks isolation, clear the IRQ_DOMAIN_FLAG_MSI_REMAP flag as well. v4: - add patch to allow the quirk hook to signal whether it was applied or not; this is necessary for hardware whose IIDR is not sufficient to identify it - use DT sub-node rather than property to describe the quirk - remove pre_its_size field, and use get_msi_base() function pointer instead v3: - add patch to pull device ID space discovery forward, so we can quirk it as well (as we already do for Cavium) - use existing quirks framework as much as possible - get rid of ITS_WORKAROUND_xxx flag: it is no longer needed after the refactoring v2: - use a 32-bit host address/size rather than a PCI address, to factor out the involvement of an SMMU (which the platform does have, but it is unclear atm if it can be exposed to the OS) - add msi_domain_flags member to move the quirk flag checks out of the common code path Ard Biesheuvel (3): drivers/irqchip: gicv3: probe device ID space before quirks handling drivers/irqchip: gic: make quirks matching conditional on init return value drivers/irqchip: gicv3: add workaround for Synquacer pre-ITS Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt | 4 + arch/arm64/Kconfig | 8 ++ drivers/irqchip/irq-gic-common.c | 5 +- drivers/irqchip/irq-gic-common.h | 2 +- drivers/irqchip/irq-gic-v3-its.c | 113 ++++++++++++++++---- 5 files changed, 110 insertions(+), 22 deletions(-) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html