From patchwork Tue Oct 22 13:22:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 177155 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp4858438ill; Tue, 22 Oct 2019 06:23:13 -0700 (PDT) X-Google-Smtp-Source: APXvYqzOpZf/EvWvbfpOwywOT4PIr0Q+0vPvAuR1w5aSAg6YE3hMKDHQR1NumtjgoZfjWMP/4GpQ X-Received: by 2002:a50:e606:: with SMTP id y6mr30973585edm.261.1571750593351; Tue, 22 Oct 2019 06:23:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571750593; cv=none; d=google.com; s=arc-20160816; b=NM+XLQuiNU5oLqJXUdY2oNbz3OjG6m3xu9w79EizooJKMgP4Kg5FVv39gf5nWA7TCG 9UZi5Mv9tU6x7/pI/m/39ixJqpdWvc3S6mTanyv3c6Jgzrw1QEgnF2awEjb9krvO2Qog ZHUSd4+bBrc5HoslMch4i6o7T5xjoCPmmE3JlyOFa/0wRZjyoIPFiuYUj6vUYideVGWs +rTLJBbuNB0EmMWQX81Yxnbv3cESnAFKZtraGfYjSjcmNF8nS1tZoCRF6nCESYl1vpZc z+PUULS60NbgqHmUFuv30lVC19/veUQFIIRWlb4qIjvsbowhDxXOyVJo/JwDISgrTfGi SElw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:dkim-signature; bh=959IPe/7SWQE1ma2r3Hx0VuoAIgKUJl/uvGTSglRrsc=; b=JYrjS7Wju4MRcg9BAnBAStp/QOGAmVtB4/n9i1L5hs4ZWancRxwXFO037uD0G0XPel rVS86FE7Qhjy6TTnO+3+CTV7438G3KQWhdI/ndmmsfbe8vIadG2Og0ukxKNAhfaymT9B C9XabwAEsyeZOmp0p8iIilsnoi6WjOx2F2ugoss6FFrV9gmEXIpR3VAbsciyP75WmhLY C3unNU/3W/AxabNPrVcPhbcXKHfoLUFwuOwA8kOaZCRxciwU7BAYNeuLNBxhUNYVRfjp DD028+14guyh1f7u6ug/T3Vra9HA5oYw7IkALE5jK8lvMQeT2H4P4ouqocRRZcKh+9fs +t0g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="WFSGM0/V"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g21si12304837edq.289.2019.10.22.06.23.13; Tue, 22 Oct 2019 06:23:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="WFSGM0/V"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732024AbfJVNXM (ORCPT + 8 others); Tue, 22 Oct 2019 09:23:12 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:42580 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731900AbfJVNXM (ORCPT ); Tue, 22 Oct 2019 09:23:12 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9MDN92i086982; Tue, 22 Oct 2019 08:23:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571750589; bh=959IPe/7SWQE1ma2r3Hx0VuoAIgKUJl/uvGTSglRrsc=; h=From:To:CC:Subject:Date; b=WFSGM0/V6TqcnEVBMWnHd9yjA1CsWzQVexn9Dwql6jFzaqhnHObk+oVDqh6KylkDS SBao+6htLGAj4CbO7sJcq3RnXima0qaekXlFkoYOODcgCXUcrPVY30oMlo7keHiZ8D 7M+GSVJI2RmbwvZvseo//yoAC8z+OZEEwdFgWE6Y= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9MDN9Xg068061 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 22 Oct 2019 08:23:09 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 22 Oct 2019 08:23:08 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 22 Oct 2019 08:22:59 -0500 Received: from lta0400828a.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9MDMplY126427; Tue, 22 Oct 2019 08:22:52 -0500 From: Roger Quadros To: CC: , , , , , , Roger Quadros Subject: [PATCH 0/3] phy: cadence: j721e-wiz: Add Type-C plug flip support Date: Tue, 22 Oct 2019 16:22:46 +0300 Message-ID: <20191022132249.869-1-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi, On J721e platform, the 2 lanes of SERDES PHY are used to achieve USB Type-C plug flip support without any additional MUX component by using a lane swap feature. However, the driver needs to know the Type-C plug orientation before it can decide whether to swap the lanes or not. This is achieved via a GPIO named DIR. Another constraint is that the lane swap must happen only when the PHY is in inactive state. This is achieved by sampling the GPIO and programming the lane swap before bringing the PHY out of reset. This series adds support to read the GPIO and accordingly program the Lane swap for Type-C plug flip support. Series must be applied on top of https://lkml.org/lkml/2019/10/16/517 cheers, -roger Roger Quadros (3): phy: cadence: Sierra: add phy_reset hook dt-bindings: phy: ti,phy-j721e-wiz: Add Type-C dir GPIO phy: ti: j721e-wiz: Manage typec-gpio-dir .../bindings/phy/ti,phy-j721e-wiz.txt | 9 ++++ drivers/phy/cadence/phy-cadence-sierra.c | 10 +++++ drivers/phy/ti/phy-j721e-wiz.c | 41 +++++++++++++++++++ 3 files changed, 60 insertions(+) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. 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