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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id f7sm3135396otl.60.2020.06.22.00.59.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jun 2020 00:59:44 -0700 (PDT) From: Bjorn Andersson To: Andy Gross , Bjorn Andersson , Ohad Ben-Cohen , Baolin Wang , Rob Herring Cc: linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 0/4] hwspinlock: qcom: Allow dropping the intermediate TCSR mutex syscon Date: Mon, 22 Jun 2020 00:59:52 -0700 Message-Id: <20200622075956.171058-1-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In modern Qualcomm platforms the mutex region of the TCSR is forked off into its own block, all with a offset of 0 and stride of 4096, and in some of these platforms no other registers in this region is accessed from Linux. Update the binding and the implementation to allow the TCSR mutex to be represented without an intermediate syscon node. Bjorn Andersson (4): dt-bindings: hwlock: qcom: Migrate binding to YAML dt-bindings: hwlock: qcom: Allow device on mmio bus hwspinlock: qcom: Allow mmio usage in addition to syscon arm64: dts: qcom: sm8250: Drop tcsr_mutex syscon .../bindings/hwlock/qcom-hwspinlock.txt | 39 ----------- .../bindings/hwlock/qcom-hwspinlock.yaml | 65 +++++++++++++++++ arch/arm64/boot/dts/qcom/sm8250.dtsi | 17 ++--- drivers/hwspinlock/qcom_hwspinlock.c | 70 ++++++++++++++----- 4 files changed, 125 insertions(+), 66 deletions(-) delete mode 100644 Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.txt create mode 100644 Documentation/devicetree/bindings/hwlock/qcom-hwspinlock.yaml -- 2.26.2 Reviewed-by: Rob Herring