From patchwork Tue Feb 2 07:16:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 374599 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp1978967jah; Mon, 1 Feb 2021 23:22:43 -0800 (PST) X-Google-Smtp-Source: ABdhPJzKUB7aNhTJyj//O8asO6Y2TnIsjX6dKxMEj6cUEfGLfmPUxdXzH5CdHGfouiarbmi+xFcD X-Received: by 2002:a05:6402:3589:: with SMTP id y9mr22661207edc.344.1612250563687; Mon, 01 Feb 2021 23:22:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612250563; cv=none; d=google.com; s=arc-20160816; b=LmUmI8zj7xekot1LjxD9hI7ZetlmFaqbb03JlVfpTxfkU9iV0Grix0xVP3t5VcZbfa tSb6GgcohbRxS6qmF7qeI++5VOtB4k5V0s5OsxZikWP79v2e5uTmGhf5CXngH2Mf9Sal AQanTwzEO8MgOJ6XLnDAg6hldgYn4UYrjBGlg5lFmtI8PC6dOzgcMRZyJxSUMRcbhn8D GSEwCG5RHVxyuOo51Xety54i6s55myrDSzW6AihXCdBpcqfTCZKM4Zrx+26IwQ5lrNy6 iQZwPOzZJ3fVecSxYfOhmbO/mnlvTqaqilIWNUGB3dJOeeRr1zKahHqCGlLSTzDicc1y Mt2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=MFYijVaQDivnMpoPZWAT1Dx4kyr5f/xTBaDDIa7AwwM=; b=fpIi+0GmbeE/4A9x7m7W0E+jbs727z4HUnQsJo2nLyhKcNfNHpDjw7NO4o6xZHNdPq +gCrvEC3EeynjEtLwS/h8ZquJpqYgzfeAnZzmAkd6DQ1SYUjd1bB285uPZ1XxNdHCmbc yeBNmwV9xCt5rW7yDsFpz1T72BU+oJ4f+/xXKn3OiYCEoU961CbeFzlxGwy57r1c3r4h vWJoVpM58pHcIfIyJ/+vfCwRBbk0tUzCl6Iyhk4FKNIz9m7BWgrQ2nFVrvDUin2x4uKT scoVubMg0MRbPNneWBErnQLY4D5UFcG/S4IGM2eeo+JTyNGI4pthZNEYK87VE9ypmOZ8 ehDw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id w3si11914746edt.463.2021.02.01.23.22.43; Mon, 01 Feb 2021 23:22:43 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231560AbhBBHWI (ORCPT + 6 others); Tue, 2 Feb 2021 02:22:08 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:12003 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231685AbhBBHWH (ORCPT ); Tue, 2 Feb 2021 02:22:07 -0500 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4DVGRW1LtdzjHTR; Tue, 2 Feb 2021 15:20:07 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.176.220) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.498.0; Tue, 2 Feb 2021 15:21:17 +0800 From: Zhen Lei To: Russell King , Greg Kroah-Hartman , Will Deacon , "Haojian Zhuang" , Arnd Bergmann , "Rob Herring" , Wei Xu , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH v7 0/4] ARM: Add support for Hisilicon Kunpeng L3 cache controller Date: Tue, 2 Feb 2021 15:16:44 +0800 Message-ID: <20210202071648.1776-1-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.174.176.220] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org v6 --> v7: 1. Change all readl()/writel() to _relaxed(), add the corresponding description to the code. 2. Delete the unnecessary spinlock protection in l3cache_init(). v5 --> v6: 1. Use raw_spin_lock_irqsave() instead of spin_lock_irqsave() 2. Move the macros defined in cache-kunpeng-l3.h into cache-kunpeng-l3.c, and delete that header file. 3. In some places, replace readl()/writel() with readl_relaxed()/writel_relaxed() to improve performance without affecting functions. 4. Returns 0 instead of an error code when Kunpeng L3 Cache matching failed. Thank you for Arnd's review comments and Russell's help. v4 --> v5: 1. Add SoC macro ARCH_KUNPENG50X, and the Kunpeng L3 cache controller only enabled on that platform. 2. Require the compatible string of the Kunpeng L3 cache controller must have a relevant name on a specific SoC. For example: compatible = "hisilicon,kunpeng509-l3cache", "hisilicon,kunpeng-l3cache"; v3 --> v4: Rename the compatible string from "hisilicon,l3cache" to "hisilicon,kunpeng-l3cache". Then adjust the file name, configuration option name, and description accordingly. v2 --> v3: Add Hisilicon L3 cache controller driver and its document. That's: patch 2-3. v1 --> v2: Discard the middle-tier functions and do silent narrowing cast in the outcache hook functions. For example: -static void l2c220_inv_range(unsigned long start, unsigned long end) +static void l2c220_inv_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; v1: Do cast phys_addr_t to unsigned long by adding a middle-tier function. For example: -static void l2c220_inv_range(unsigned long start, unsigned long end) +static void __l2c220_inv_range(unsigned long start, unsigned long end) { ... } +static void l2c220_inv_range(phys_addr_t start, phys_addr_t end) +{ + __l2c220_inv_range(start, end); +} Zhen Lei (4): ARM: LPAE: Use phys_addr_t instead of unsigned long in outercache hooks ARM: hisi: add support for Kunpeng50x SoC dt-bindings: arm: hisilicon: Add binding for Kunpeng L3 cache controller ARM: Add support for Hisilicon Kunpeng L3 cache controller .../arm/hisilicon/kunpeng-l3cache.yaml | 40 ++++ arch/arm/include/asm/outercache.h | 6 +- arch/arm/mach-hisi/Kconfig | 6 + arch/arm/mm/Kconfig | 10 + arch/arm/mm/Makefile | 1 + arch/arm/mm/cache-feroceon-l2.c | 15 +- arch/arm/mm/cache-kunpeng-l3.c | 178 ++++++++++++++++++ arch/arm/mm/cache-l2x0.c | 50 +++-- arch/arm/mm/cache-tauros2.c | 15 +- arch/arm/mm/cache-uniphier.c | 6 +- arch/arm/mm/cache-xsc3l2.c | 12 +- 11 files changed, 310 insertions(+), 29 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml create mode 100644 arch/arm/mm/cache-kunpeng-l3.c -- 2.26.0.106.g9fadedd