From patchwork Thu Aug 19 08:00:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ChiaWei Wang X-Patchwork-Id: 499917 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9A37C4338F for ; Thu, 19 Aug 2021 08:00:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8667C6113A for ; Thu, 19 Aug 2021 08:00:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236938AbhHSIBR (ORCPT ); Thu, 19 Aug 2021 04:01:17 -0400 Received: from twspam01.aspeedtech.com ([211.20.114.71]:38568 "EHLO twspam01.aspeedtech.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232017AbhHSIBR (ORCPT ); Thu, 19 Aug 2021 04:01:17 -0400 Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 17J7gOT4024037; Thu, 19 Aug 2021 15:42:24 +0800 (GMT-8) (envelope-from chiawei_wang@aspeedtech.com) Received: from ChiaWeiWang-PC.aspeed.com (192.168.2.66) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 19 Aug 2021 16:00:36 +0800 From: Chia-Wei Wang To: , , , , , , , CC: Subject: [PATCH v2 0/5] arm: aspeed: Add eSPI support Date: Thu, 19 Aug 2021 16:00:35 +0800 Message-ID: <20210819080040.31242-1-chiawei_wang@aspeedtech.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [192.168.2.66] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 17J7gOT4024037 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch series add the driver support for the eSPI controller of Aspeed 5/6th generation SoCs. This controller is a slave device communicating with a master over Enhanced Serial Peripheral Interface (eSPI). It supports all of the 4 eSPI channels, namely peripheral, virtual wire, out-of-band, and flash, and operates at max frequency of 66MHz. v2: - remove irqchip implementation - merge per-channel drivers into single one to avoid the racing issue among eSPI handshake process and driver probing. Chia-Wei Wang (5): dt-bindings: aspeed: Add eSPI controller MAINTAINER: Add ASPEED eSPI driver entry clk: aspeed: Add eSPI reset bit soc: aspeed: Add eSPI driver ARM: dts: aspeed: Add eSPI node .../devicetree/bindings/soc/aspeed/espi.yaml | 158 +++++ MAINTAINERS | 9 + arch/arm/boot/dts/aspeed-g6.dtsi | 17 + drivers/soc/aspeed/Kconfig | 11 + drivers/soc/aspeed/Makefile | 1 + drivers/soc/aspeed/aspeed-espi-ctrl.c | 206 ++++++ drivers/soc/aspeed/aspeed-espi-ctrl.h | 304 +++++++++ drivers/soc/aspeed/aspeed-espi-flash.h | 380 +++++++++++ drivers/soc/aspeed/aspeed-espi-ioc.h | 153 +++++ drivers/soc/aspeed/aspeed-espi-oob.h | 611 ++++++++++++++++++ drivers/soc/aspeed/aspeed-espi-perif.h | 512 +++++++++++++++ drivers/soc/aspeed/aspeed-espi-vw.h | 142 ++++ include/dt-bindings/clock/ast2600-clock.h | 1 + 13 files changed, 2505 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/aspeed/espi.yaml create mode 100644 drivers/soc/aspeed/aspeed-espi-ctrl.c create mode 100644 drivers/soc/aspeed/aspeed-espi-ctrl.h create mode 100644 drivers/soc/aspeed/aspeed-espi-flash.h create mode 100644 drivers/soc/aspeed/aspeed-espi-ioc.h create mode 100644 drivers/soc/aspeed/aspeed-espi-oob.h create mode 100644 drivers/soc/aspeed/aspeed-espi-perif.h create mode 100644 drivers/soc/aspeed/aspeed-espi-vw.h