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[v4,00/16] Multiple addition and improvement to ipq8064 gcc

Message ID 20220217235703.26641-1-ansuelsmth@gmail.com
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Series Multiple addition and improvement to ipq8064 gcc | expand

Message

Christian Marangi Feb. 17, 2022, 11:56 p.m. UTC 
This is an attempt in making the ipq8064 SoC actually usable. Currently
many feature are missing for this SoC and devs user off-the-tree patches
to make it work (example patch for missing clock, patch for cpufreq
driver, patch to add missing node in the dts)

I notice there was some work in modernizing the gcc driver for other
qcom target but this wasn't done for ipq806x. This does exactly this, we
drop any parent_names stuff and we switch to the parent_data way. We
also drop the pxo and cxo source clk from gcc driver and we refer to the
dts for it.

This also add all the missing feature for the nss cores and the
cryptoengine in them. It does also introduce the required flags to make
the RPM actually work and NOT reject any command. There was an attempt
in declaring these clock as core clock in the dts but this ends up in no
serial as the kernel makes these clock not accessible. We just want to
make the kernel NOT disable them if unused nothing more.

At the end we update the ipq8064 dtsi to add the pxo and cxo tag and
declare them in gcc and also fix a problem with tsens probe.

v4:
- Drop drivers in all the patches.
- Introduce floor ops for sdc
- gcc.yaml to gcc-other.yaml
- gcc-common.yaml to gcc.yaml
v3:
- Rework Documentation with Rob suggestions
v2:
- Fix error from Rob bot.
- Add additional commits to make qcom,gcc.yaml a template
- Squash parent_hws patch with the modernize patch
- Create gcc_pxo instead of using long define.

Ansuel Smith (16):
  dt-bindings: clock: split qcom,gcc.yaml to common and specific schema
  dt-bindings: clock: simplify qcom,gcc-apq8064 Documentation
  dt-bindings: clock: Document qcom,gcc-ipq8064 binding
  clk: qcom: gcc-ipq806x: fix wrong naming for gcc_pxo_pll8_pll0
  clk: qcom: gcc-ipq806x: convert parent_names to parent_data
  clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents
  clk: qcom: gcc-ipq806x: drop hardcoded pxo and cxo source clk
  clk: qcom: gcc-ipq806x: add additional freq nss cores
  clk: qcom: gcc-ipq806x: add unusued flag for critical clock
  clk: qcom: clk-rcg: add clk_rcg_floor_ops ops
  clk: qcom: gcc-ipq806x: add additional freq for sdc table
  dt-bindings: clock: add ipq8064 ce5 clk define
  clk: qcom: gcc-ipq806x: add CryptoEngine clocks
  dt-bindings: reset: add ipq8064 ce5 resets
  clk: qcom: gcc-ipq806x: add CryptoEngine resets
  ARM: dts: qcom: Add syscon and cxo/pxo clock to gcc node for ipq8064

 .../bindings/clock/qcom,gcc-apq8064.yaml      |  29 +-
 .../bindings/clock/qcom,gcc-ipq8064.yaml      |  76 +++
 .../bindings/clock/qcom,gcc-other.yaml        |  70 ++
 .../devicetree/bindings/clock/qcom,gcc.yaml   |  63 +-
 arch/arm/boot/dts/qcom-ipq8064.dtsi           |   8 +-
 drivers/clk/qcom/clk-rcg.c                    |  24 +
 drivers/clk/qcom/gcc-ipq806x.c                | 640 +++++++++++++-----
 include/dt-bindings/clock/qcom,gcc-ipq806x.h  |   5 +-
 include/dt-bindings/reset/qcom,gcc-ipq806x.h  |   5 +
 9 files changed, 670 insertions(+), 250 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml