From patchwork Thu Sep 8 11:17:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 604000 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 808F1C54EE9 for ; Thu, 8 Sep 2022 11:18:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230240AbiIHLSA (ORCPT ); Thu, 8 Sep 2022 07:18:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59674 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229695AbiIHLSA (ORCPT ); Thu, 8 Sep 2022 07:18:00 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 29D87ED3B5; Thu, 8 Sep 2022 04:17:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1662635878; x=1694171878; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=j5a61ZKFUAdC26BITQdeai++FyrcXlsWeUVOGnGDHZk=; b=cYHvVpNgooS3CGxH+y9cD4vTSAPlAS3mnqihgFAkzIfAg8Tmoga1vsBn GdckT7dbMS5iJxzliNnSGhME0m5mqJ6momoOzrmYQ2dgAq5CRAw8aOgVJ JlSCa4racHKf4uH9NPrlZ3JOdAtgO0s2/rqJSFVJI3Oqu+AghIwh4noko sRGoTEydk7ZJmfBe958NGblYP2ktpbOw8sywuiVBBkixQye2C9RC6EUL8 5Dd4JNAtz+26ejnQhMPEh7M2bmC/RYPdqAFPr2tHCc7Ajf5iQ7he1tsyg eF+G7JPkQWLmYHRGPvWUjo1OWFecVIdtekLaBK/crMTnJcClUrA7oykIl g==; X-IronPort-AV: E=Sophos;i="5.93,299,1654585200"; d="scan'208";a="179670048" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Sep 2022 04:17:58 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 8 Sep 2022 04:17:57 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 8 Sep 2022 04:17:54 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , Subject: [PATCH v4 00/10] New PolarFire SoC devkit devicetrees & 22.09 reference design updates Date: Thu, 8 Sep 2022 12:17:03 +0100 Message-ID: <20220908111712.665287-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hey all, Some 6.1 targeted changes here. Firstly, two new dev kits (one first-party & one from Aries Embedded). They've been sitting in our vendor tree, so are being sent where they belong. Secondly, another release of our reference design for the Icicle kit is due in September. Usually these do not really change much for the devicetree, but this time around a pair of changes impact the memory map. The first of these is adding dma-ranges to the pcie controller. The controller had some issues to begin with & with the current reference design (v2022.05) would not work with mainline Linux nor has it since reference design v2021.08. A combination of the property, a change to the FPGA design & a small fix to the driver will get it working with mainline again. The other non-backwards compatible change to the reference design is moves of the peripherals instantiated in the fabric. Currently they are fairly spread out & a common complaint has been that this leaves little room in the fic3 section of the memory map for custom peripherals without removing the existing ones. This series depends on [0] so as not to add dtbs_check warnings. The fabric clock support is added by [1]. Thanks, Conor. Changes since v3: - add an extra patch reducing the fic3 clock rate Changes since v2: - drop the sd & emmc versions of the aries devicetree - remove a extra newline Changes since v1: - made the polarberry part of an enum in patch 1 0 - https://lore.kernel.org/linux-gpio/20220825143522.3102546-1-conor.dooley@microchip.com/ 1 - https://lore.kernel.org/linux-clk/20220824093342.187844-1-conor.dooley@microchip.com/ Conor Dooley (8): dt-bindings: riscv: microchip: document icicle reference design dt-bindings: riscv: microchip: document the aries m100pfsevp riscv: dts: microchip: add pci dma ranges for the icicle kit riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi riscv: dts: microchip: icicle: update pci address properties riscv: dts: microchip: icicle: re-jig fabric peripheral addresses riscv: dts: microchip: reduce the fic3 clock rate riscv: dts: microchip: add a devicetree for aries' m100pfsevp Shravan Chippa (1): dt-bindings: riscv: microchip: document the sev kit Vattipalli Praveen (1): riscv: dts: microchip: add sevkit device tree .../devicetree/bindings/riscv/microchip.yaml | 20 +- arch/riscv/boot/dts/microchip/Makefile | 2 + .../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 44 ++++- .../boot/dts/microchip/mpfs-icicle-kit.dts | 3 +- .../dts/microchip/mpfs-m100pfs-fabric.dtsi | 45 +++++ .../boot/dts/microchip/mpfs-m100pfsevp.dts | 179 ++++++++++++++++++ .../dts/microchip/mpfs-polarberry-fabric.dtsi | 29 +++ .../dts/microchip/mpfs-sev-kit-fabric.dtsi | 45 +++++ .../riscv/boot/dts/microchip/mpfs-sev-kit.dts | 145 ++++++++++++++ arch/riscv/boot/dts/microchip/mpfs.dtsi | 29 --- 10 files changed, 499 insertions(+), 42 deletions(-) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts