[PATCHv2,0/3] mmc: socfpga: add method to configure clk-phase

Hi,

This is version 2 of the patchset to configure the clk-phase for the
SDMMC controller on SoCFPGA platforms.

Updates from v1:
- Documented "altr,sysmgr-syscon" binding
- Cleaned up dw_mci_socfpga_priv_init() to get the "clk-phase-sd-hs"
  from the DTS. Ulf Hanson recommended using mmc_of_parse_clk_phase() in
  this function, however, I found that using mmc_of_parse_clk_phase() is a
  bit more complicated than just reading the "clk-phase-sd-hs" from the
  DTS. Here are the reasons:
 	- The call to mmc_of_parse_clk_phase() takes the struct mmc_host
 	  *host structure, and in the dw_mmc driver, and this structure
	  does not get populated until at the very end of the dw_mci_probe
	  function, after dw_mci_init_slot() gets called.
	- Also, in order to correctly extract the
	  phase_map.phase[timing], we need to wait until set_ios() is
	  called in order to get the host->timing parameter so it can be used for
	  the clock phase array.

Dinh Nguyen (3):
  dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon"
  arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node
  mmc: dw_mmc-pltfm: socfpga: add method to configure clk-phase

 .../bindings/mmc/synopsys-dw-mshc.yaml        |  8 ++++
 .../boot/dts/altera/socfpga_stratix10.dtsi    |  1 +
 .../dts/altera/socfpga_stratix10_socdk.dts    |  1 +
 arch/arm64/boot/dts/intel/socfpga_agilex.dtsi |  1 +
 .../boot/dts/intel/socfpga_agilex_socdk.dts   |  1 +
 .../boot/dts/intel/socfpga_n5x_socdk.dts      |  1 +
 drivers/mmc/host/dw_mmc-pltfm.c               | 41 ++++++++++++++++++-
 7 files changed, 53 insertions(+), 1 deletion(-)

On 23/09/2022 00:03, Dinh Nguyen wrote:
> Document the optional "altr,sysmgr-syscon" binding that is used to
> access the System Manager register that controls the SDMMC clock
> phase.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

Thank you for your patch. There is something to discuss/improve.

> ---
> v2: added
> ---
>  .../devicetree/bindings/mmc/synopsys-dw-mshc.yaml    | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml
> index ae6d6fca79e2..aece6a337262 100644
> --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml
> +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml
> @@ -38,6 +38,18 @@ properties:
>        - const: biu
>        - const: ciu
>  
> +  altr,sysmgr-syscon:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +      - items:
> +          - description: phandle to the sysmgr node
> +          - description: register offset that controls the SDMMC clock phase
> +    description:
> +      Contains the phandle to System Manager block that contains
> +      the SDMMC clock-phase control register. The first value is the pointer
> +      to the sysmgr and the 2nd value is the register offset for the SDMMC
> +      clock phase register.

You need to restrict it per variant (altera). Move the allOf from top of
the file to place above unevaluatedProperties and add if:then: making it
false for other variants.

Best regards,
Krzysztof