[v3,0/3] mtd: rawnand: marvell: add support for AC5 SoC

This series adds support for the NAND Flash Controller on the AC5/AC5X SOC. Its
dependent series are all in mainline now so this should apply cleanly on top of
that.

I've tried to stick to the minimal changes required to get the NFC working on
the board I have (AC5X + S34ML02G2). Marvell's SDK has hard coded tables of
ndtr values for the different timing modes but so far that seems unnecessary.

Chris Packham (3):
  dt-bindings: mtd: Add AC5 specific binding
  arm64: dts: marvell: Add NAND flash controller to AC5
  mtd: rawnand: marvell: add support for AC5 SoC

 .../bindings/mtd/marvell,nand-controller.yaml    |  1 +
 arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi    | 16 ++++++++++++++++
 drivers/mtd/nand/raw/Kconfig                     |  2 +-
 drivers/mtd/nand/raw/marvell_nand.c              | 16 ++++++++++++++++
 4 files changed, 34 insertions(+), 1 deletion(-)

Hi Chris,

chris.packham@alliedtelesis.co.nz wrote on Mon,  3 Jul 2023 15:50:42
+1200:

> Add binding for AC5 SoC. This SoC only supports NAND SDR timings up to
> mode 3 so a specific compatible value is needed.
> 
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>

I need DT-binding maintainer's ack to take this patch, but this commit
did not receive feedback (positive of negative) from them and is no
longer in their patchwork. Can you please resend the series?

The other patches LGTM.


> ---
> 
> Notes:
>     Changes in v3:
>     - Collect ack from Conor
>     Changes in v2:
>     - Keep compatibles in alphabetical order
>     - Explain AC5 limitations in commit message
> 
>  .../devicetree/bindings/mtd/marvell,nand-controller.yaml         | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml
> index a10729bb1840..1ecea848e8b9 100644
> --- a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml
> +++ b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml
> @@ -16,6 +16,7 @@ properties:
>            - const: marvell,armada-8k-nand-controller
>            - const: marvell,armada370-nand-controller
>        - enum:
> +          - marvell,ac5-nand-controller
>            - marvell,armada370-nand-controller
>            - marvell,pxa3xx-nand-controller
>        - description: legacy bindings


Thanks,
Miquèl

On Wed, Jul 12, 2023 at 02:32:20PM +0200, Miquel Raynal wrote:
> Hi Chris,
> 
> chris.packham@alliedtelesis.co.nz wrote on Mon,  3 Jul 2023 15:50:42
> +1200:
> 
> > Add binding for AC5 SoC. This SoC only supports NAND SDR timings up to
> > mode 3 so a specific compatible value is needed.
> > 
> > Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> 
> I need DT-binding maintainer's ack to take this patch, but this commit
> did not receive feedback (positive of negative) from them and is no
> longer in their patchwork. Can you please resend the series?

You have one ;)

https://docs.kernel.org/process/maintainers.html?highlight=conor+dooley#open-firmware-and-flattened-device-tree-bindings

Hi Miquel,

On 13/07/23 00:32, Miquel Raynal wrote:
> Hi Chris,
>
> chris.packham@alliedtelesis.co.nz wrote on Mon,  3 Jul 2023 15:50:42
> +1200:
>
>> Add binding for AC5 SoC. This SoC only supports NAND SDR timings up to
>> mode 3 so a specific compatible value is needed.
>>
>> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
>> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> I need DT-binding maintainer's ack to take this patch, but this commit
> did not receive feedback (positive of negative) from them and is no
> longer in their patchwork. Can you please resend the series?

Conor's ack was provided on

https://lore.kernel.org/linux-mtd/20230626-immunity-lagged-eaae0182ad0c@spud/

Is this sufficient? I'm happy to resend if needed.

>
> The other patches LGTM.
>
>
>> ---
>>
>> Notes:
>>      Changes in v3:
>>      - Collect ack from Conor
>>      Changes in v2:
>>      - Keep compatibles in alphabetical order
>>      - Explain AC5 limitations in commit message
>>
>>   .../devicetree/bindings/mtd/marvell,nand-controller.yaml         | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml
>> index a10729bb1840..1ecea848e8b9 100644
>> --- a/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml
>> +++ b/Documentation/devicetree/bindings/mtd/marvell,nand-controller.yaml
>> @@ -16,6 +16,7 @@ properties:
>>             - const: marvell,armada-8k-nand-controller
>>             - const: marvell,armada370-nand-controller
>>         - enum:
>> +          - marvell,ac5-nand-controller
>>             - marvell,armada370-nand-controller
>>             - marvell,pxa3xx-nand-controller
>>         - description: legacy bindings
>
> Thanks,
> Miquèl

Hi Conor,

conor@kernel.org wrote on Wed, 12 Jul 2023 19:13:02 +0100:

> On Wed, Jul 12, 2023 at 02:32:20PM +0200, Miquel Raynal wrote:
> > Hi Chris,
> > 
> > chris.packham@alliedtelesis.co.nz wrote on Mon,  3 Jul 2023 15:50:42
> > +1200:
> >   
> > > Add binding for AC5 SoC. This SoC only supports NAND SDR timings up to
> > > mode 3 so a specific compatible value is needed.
> > > 
> > > Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> > > Acked-by: Conor Dooley <conor.dooley@microchip.com>  
> > 
> > I need DT-binding maintainer's ack to take this patch, but this commit
> > did not receive feedback (positive of negative) from them and is no
> > longer in their patchwork. Can you please resend the series?  
> 
> You have one ;)
> 
> https://docs.kernel.org/process/maintainers.html?highlight=conor+dooley#open-firmware-and-flattened-device-tree-bindings

\o/

Love that, thanks for stepping-up and good luck!

Thanks,
Miquèl