| Message ID | 20230712092007.31013-1-xingyu.wu@starfivetech.com |
|---|---|
| Headers | show |
| Series | Add STG/ISP/VOUT clock and reset drivers for StarFive JH7110 | expand |
On Wed, 12 Jul 2023 at 11:22, Xingyu Wu <xingyu.wu@starfivetech.com> wrote: > > Add bindings for the System-Top-Group clock and reset generator (STGCRG) > on the JH7110 RISC-V SoC by StarFive Ltd. > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> > --- > .../clock/starfive,jh7110-stgcrg.yaml | 82 +++++++++++++++++++ > .../dt-bindings/clock/starfive,jh7110-crg.h | 34 ++++++++ > .../dt-bindings/reset/starfive,jh7110-crg.h | 28 +++++++ > 3 files changed, 144 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml > > diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml > new file mode 100644 > index 000000000000..b64ccd84200a > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml > @@ -0,0 +1,82 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: StarFive JH7110 System-Top-Group Clock and Reset Generator > + > +maintainers: > + - Xingyu Wu <xingyu.wu@starfivetech.com> > + > +properties: > + compatible: > + const: starfive,jh7110-stgcrg > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: Main Oscillator (24 MHz) > + - description: HIFI4 core > + - description: STG AXI/AHB > + - description: USB (125 MHz) > + - description: CPU Bus > + - description: HIFI4 Axi > + - description: NOC STG Bus > + - description: APB Bus > + > + clock-names: > + items: > + - const: osc > + - const: hifi4_core > + - const: stg_axiahb > + - const: usb_125m > + - const: cpu_bus > + - const: hifi4_axi > + - const: nocstg_bus > + - const: apb_bus > + > + '#clock-cells': > + const: 1 > + description: > + See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices. > + > + '#reset-cells': > + const: 1 > + description: > + See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices. > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - '#clock-cells' > + - '#reset-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/starfive,jh7110-crg.h> > + > + stgcrg: clock-controller@10230000 { > + compatible = "starfive,jh7110-stgcrg"; > + reg = <0x10230000 0x10000>; > + clocks = <&osc>, > + <&syscrg JH7110_SYSCLK_HIFI4_CORE>, > + <&syscrg JH7110_SYSCLK_STG_AXIAHB>, > + <&syscrg JH7110_SYSCLK_USB_125M>, > + <&syscrg JH7110_SYSCLK_CPU_BUS>, > + <&syscrg JH7110_SYSCLK_HIFI4_AXI>, > + <&syscrg JH7110_SYSCLK_NOCSTG_BUS>, > + <&syscrg JH7110_SYSCLK_APB_BUS>; > + clock-names = "osc", "hifi4_core", > + "stg_axiahb", "usb_125m", > + "cpu_bus", "hifi4_axi", > + "nocstg_bus", "apb_bus"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h > index 06257bfd9ac1..6c8e8b4cf1f6 100644 > --- a/include/dt-bindings/clock/starfive,jh7110-crg.h > +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h > @@ -1,6 +1,7 @@ > /* SPDX-License-Identifier: GPL-2.0 OR MIT */ > /* > * Copyright 2022 Emil Renner Berthing <kernel@esmil.dk> > + * Copyright 2022 StarFive Technology Co., Ltd. > */ > > #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ > @@ -218,4 +219,37 @@ > > #define JH7110_AONCLK_END 14 > > +/* STGCRG clocks */ > +#define JH7110_STGCLK_HIFI4_CLK_CORE 0 > +#define JH7110_STGCLK_USB0_APB 1 > +#define JH7110_STGCLK_USB0_UTMI_APB 2 > +#define JH7110_STGCLK_USB0_AXI 3 > +#define JH7110_STGCLK_USB0_LPM 4 > +#define JH7110_STGCLK_USB0_STB 5 > +#define JH7110_STGCLK_USB0_APP_125 6 > +#define JH7110_STGCLK_USB0_REFCLK 7 > +#define JH7110_STGCLK_PCIE0_AXI_MST0 8 > +#define JH7110_STGCLK_PCIE0_APB 9 > +#define JH7110_STGCLK_PCIE0_TL 10 > +#define JH7110_STGCLK_PCIE1_AXI_MST0 11 > +#define JH7110_STGCLK_PCIE1_APB 12 > +#define JH7110_STGCLK_PCIE1_TL 13 > +#define JH7110_STGCLK_PCIE_SLV_MAIN 14 > +#define JH7110_STGCLK_SEC_AHB 15 > +#define JH7110_STGCLK_SEC_MISC_AHB 16 > +#define JH7110_STGCLK_GRP0_MAIN 17 > +#define JH7110_STGCLK_GRP0_BUS 18 > +#define JH7110_STGCLK_GRP0_STG 19 > +#define JH7110_STGCLK_GRP1_MAIN 20 > +#define JH7110_STGCLK_GRP1_BUS 21 > +#define JH7110_STGCLK_GRP1_STG 22 > +#define JH7110_STGCLK_GRP1_HIFI 23 > +#define JH7110_STGCLK_E2_RTC 24 > +#define JH7110_STGCLK_E2_CORE 25 > +#define JH7110_STGCLK_E2_DBG 26 > +#define JH7110_STGCLK_DMA1P_AXI 27 > +#define JH7110_STGCLK_DMA1P_AHB 28 > + > +#define JH7110_STGCLK_END 29 > + > #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */ > diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h > index d78e38690ceb..4e96ab81dd8e 100644 > --- a/include/dt-bindings/reset/starfive,jh7110-crg.h > +++ b/include/dt-bindings/reset/starfive,jh7110-crg.h > @@ -1,6 +1,7 @@ > /* SPDX-License-Identifier: GPL-2.0 OR MIT */ > /* > * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk> > + * Copyright (C) 2022 StarFive Technology Co., Ltd. > */ > > #ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ > @@ -151,4 +152,31 @@ > > #define JH7110_AONRST_END 8 > > +/* STGCRG resets */ > +#define JH7110_STGRST_SYSCON 0 > +#define JH7110_STGRST_HIFI4_CORE 1 > +#define JH7110_STGRST_HIFI4_AXI 2 > +#define JH7110_STGRST_SEC_AHB 3 > +#define JH7110_STGRST_E24_CORE 4 > +#define JH7110_STGRST_DMA1P_AXI 5 > +#define JH7110_STGRST_DMA1P_AHB 6 > +#define JH7110_STGRST_USB0_AXI 7 > +#define JH7110_STGRST_USB0_APB 8 > +#define JH7110_STGRST_USB0_UTMI_APB 9 > +#define JH7110_STGRST_USB0_PWRUP 10 > +#define JH7110_STGRST_PCIE0_AXI_MST0 11 > +#define JH7110_STGRST_PCIE0_AXI_SLV0 12 > +#define JH7110_STGRST_PCIE0_AXI_SLV 13 > +#define JH7110_STGRST_PCIE0_BRG 14 > +#define JH7110_STGRST_PCIE0_CORE 15 > +#define JH7110_STGRST_PCIE0_APB 16 > +#define JH7110_STGRST_PCIE1_AXI_MST0 17 > +#define JH7110_STGRST_PCIE1_AXI_SLV0 18 > +#define JH7110_STGRST_PCIE1_AXI_SLV 19 > +#define JH7110_STGRST_PCIE1_BRG 20 > +#define JH7110_STGRST_PCIE1_CORE 21 > +#define JH7110_STGRST_PCIE1_APB 22 > + > +#define JH7110_STGRST_END 23 > + > #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */ > -- > 2.25.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Wed, 12 Jul 2023 at 11:22, Xingyu Wu <xingyu.wu@starfivetech.com> wrote: > > Add new struct members and auxiliary_device_id of resets to support > System-Top-Group, Image-Signal-Process and Video-Output on the StarFive > JH7110 SoC. > > Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> > --- > .../reset/starfive/reset-starfive-jh7110.c | 30 +++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/drivers/reset/starfive/reset-starfive-jh7110.c b/drivers/reset/starfive/reset-starfive-jh7110.c > index 2d26ae95c8cc..29a43f0f2ad6 100644 > --- a/drivers/reset/starfive/reset-starfive-jh7110.c > +++ b/drivers/reset/starfive/reset-starfive-jh7110.c > @@ -31,6 +31,24 @@ static const struct jh7110_reset_info jh7110_aon_info = { > .status_offset = 0x3C, > }; > > +static const struct jh7110_reset_info jh7110_stg_info = { > + .nr_resets = JH7110_STGRST_END, > + .assert_offset = 0x74, > + .status_offset = 0x78, > +}; > + > +static const struct jh7110_reset_info jh7110_isp_info = { > + .nr_resets = JH7110_ISPRST_END, > + .assert_offset = 0x38, > + .status_offset = 0x3C, > +}; > + > +static const struct jh7110_reset_info jh7110_vout_info = { > + .nr_resets = JH7110_VOUTRST_END, > + .assert_offset = 0x48, > + .status_offset = 0x4C, > +}; > + > static int jh7110_reset_probe(struct auxiliary_device *adev, > const struct auxiliary_device_id *id) > { > @@ -58,6 +76,18 @@ static const struct auxiliary_device_id jh7110_reset_ids[] = { > .name = "clk_starfive_jh7110_sys.rst-aon", > .driver_data = (kernel_ulong_t)&jh7110_aon_info, > }, > + { > + .name = "clk_starfive_jh7110_sys.rst-stg", > + .driver_data = (kernel_ulong_t)&jh7110_stg_info, > + }, > + { > + .name = "clk_starfive_jh7110_sys.rst-isp", > + .driver_data = (kernel_ulong_t)&jh7110_isp_info, > + }, > + { > + .name = "clk_starfive_jh7110_sys.rst-vo", > + .driver_data = (kernel_ulong_t)&jh7110_vout_info, > + }, > { /* sentinel */ } > }; > MODULE_DEVICE_TABLE(auxiliary, jh7110_reset_ids); > -- > 2.25.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Wed, 12 Jul 2023 at 11:22, Xingyu Wu <xingyu.wu@starfivetech.com> wrote: > > Add DVP and HDMI TX pixel external fixed clocks and the rates are > 74.25MHz and 297MHz. > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> > --- > .../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 8 ++++++++ > arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++ > 2 files changed, 20 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > index fa0061eb33a7..de0f40a8be93 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > @@ -38,6 +38,10 @@ gpio-restart { > }; > }; > > +&dvp_clk { > + clock-frequency = <74250000>; > +}; > + > &gmac0_rgmii_rxin { > clock-frequency = <125000000>; > }; > @@ -54,6 +58,10 @@ &gmac1_rmii_refin { > clock-frequency = <50000000>; > }; > > +&hdmitx0_pixelclk { > + clock-frequency = <297000000>; > +}; > + > &i2srx_bclk_ext { > clock-frequency = <12288000>; > }; > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi > index ec2e70011a73..e9c1e4ad71a2 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > @@ -197,6 +197,12 @@ opp-1500000000 { > }; > }; > > + dvp_clk: dvp-clock { > + compatible = "fixed-clock"; > + clock-output-names = "dvp_clk"; > + #clock-cells = <0>; > + }; > + > gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { > compatible = "fixed-clock"; > clock-output-names = "gmac0_rgmii_rxin"; > @@ -221,6 +227,12 @@ gmac1_rmii_refin: gmac1-rmii-refin-clock { > #clock-cells = <0>; > }; > > + hdmitx0_pixelclk: hdmitx0-pixel-clock { > + compatible = "fixed-clock"; > + clock-output-names = "hdmitx0_pixelclk"; > + #clock-cells = <0>; > + }; > + > i2srx_bclk_ext: i2srx-bclk-ext-clock { > compatible = "fixed-clock"; > clock-output-names = "i2srx_bclk_ext"; > -- > 2.25.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On 2023/7/13 1:01, Conor Dooley wrote: > On Wed, Jul 12, 2023 at 09:50:37AM -0700, Palmer Dabbelt wrote: >> On Wed, 12 Jul 2023 02:19:58 PDT (-0700), xingyu.wu@starfivetech.com wrote: >> > This patch serises are base on the basic JH7110 SYSCRG/AONCRG >> > drivers and add new partial clock drivers and reset supports >> > about System-Top-Group(STG), Image-Signal-Process(ISP) >> > and Video-Output(VOUT) for the StarFive JH7110 RISC-V SoC. These >> > clocks and resets could be used by DMA, VIN and Display modules. > >> Happy to take it through the RISC-V tree if folks want, but IMO it's >> probably better aimed at the clock/reset folks. Either way I'd want to give >> them a chance to ack/review it, so I'm going to drop it from my list. >> >> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> > > I had a look through it & I am generally happy with it - everything has > either an R-b from DT folk or Hal on the drivers. > I was going to propose the same thing as the PLL patchset - if Emil is > happy with it, then I intend sending Stephen a PR for the drivers & > bindings. > Thanks, I will send a new version soon with some modification from Emil's comments. Best regards, Xingyu Wu
This patch serises are base on the basic JH7110 SYSCRG/AONCRG drivers and add new partial clock drivers and reset supports about System-Top-Group(STG), Image-Signal-Process(ISP) and Video-Output(VOUT) for the StarFive JH7110 RISC-V SoC. These clocks and resets could be used by DMA, VIN and Display modules. Patches 1 and 2 are about the System-Top-Group clock and reset generator(STGCRG) part. The first patch adds docunmentation to describe STG bindings, and the second patch adds clock driver to support STG clocks and resets as auxiliary device for JH7110. Patches 3 and 4 are about the Image-Signal-Process clock and reset gennerator(ISPCRG) part. The first patch adds docunmentation to describe ISP bindings, and the second patch adds clock driver to support ISP clocks and resets as auxiliary device for JH7110. And ISP clocks should power on and enable the SYSCRG clocks first before registering. Patches 5 and 6 are about the Video-Output clock and reset generator(VOUTCRG) part. The first patch adds docunmentation to describe VOUT bindings, and the second patch adds clock driver to support VOUT clocks and resets as auxiliary device for JH7110. And VOUT clocks also should power on and enable the SYSCRG clocks first before registering. Patch 7 adds struct members to support STG/ISP/VOUT resets. Patch 8 adds external clocks which ISP and VOUT clock driver need. Patch 9 adds device node about STGCRG, ISPCRG and VOUTCRG to JH7110 dts. Changes since v6: - Rebased on the Linux 6.5-rc1. - Dropped the unnecessary selections in the Kconfig. - Dropped the patches about the PMU node and MAINTIANERS. - Add the reviews. v6: https://lore.kernel.org/all/20230518101234.143748-1-xingyu.wu@starfivetech.com/ Changes since v5: - Rebased on the Linux 6.4-rc2. - Modified the reset name about VOUTCRG to fix the error with CONFIG_FORTIFY_SOURCE=y - Added the patch about pmu node. v5: https://lore.kernel.org/all/20230424135409.6648-1-xingyu.wu@starfivetech.com/ Changes since v4: - Rebased on the lastest patches about fixing the basic clock and reset drivers. - Dropped the 'dev_set_drvdata()' in STG clock driver. - Modified the data with 'dev_set_drvdata()' in ISP/VOUT clock driver and move the struct about the data to JH7110 header file, which both ISP and VOUT clock drivers will use. v4: https://lore.kernel.org/all/20230411135558.44282-1-xingyu.wu@starfivetech.com/ Changes since v3: - Rebased on the lastest JH71X0 clock and reset driver of patchset[1] and modified the parameters of the register reset functions. - The patch 1 combined three commits on STG/ISP/VOUT resets into one. And Changed the auxiliary_device_id name from "clk_starfive_jh71x0.reset-*" to "clk_starfive_jh7110_sys.rst-*". - Added a maintainer in STARFIVE JH71X0 CLOCK DRIVERS. v3: https://lore.kernel.org/all/20230314124404.117592-1-xingyu.wu@starfivetech.com/ Changes since v2: Patch 1: - Dropped the modification of maintainers. - Modified clock and reset names in the dt-bindings header files. Patch 3: - Added 'Emil Renner Berthing' as the author. - Used 'default m' in Kconfig file. - Changed the flags of 'CLK_IGNORE_UNUSED' to 0 or 'CLK_IS_CRITICAL'. Patch 4: - Dropped the 'reset-names' property. - Shortened the clock and reset names in the dt-bindings header files. Pacth 6: - Used 'default m' in Kconfig file. - Changed the flags of 'CLK_IGNORE_UNUSED' to 0. - Set reset_control struct to a local variable because it just is used one time in probe. Pacth 7: - Dropped the 'reset-names' property. Patch 9: - Used 'default m' in Kconfig file. - Set reset_control struct to a local variable because it just is used one time in probe. Patch 10: - Changed the order of externel clock in alphanumerical order. Patch 11: - Dropped the 'reset-names' property in ispcrg and voutcrg node. v2: https://lore.kernel.org/all/20230221083323.302471-1-xingyu.wu@starfivetech.com/ Changes since v1: - Modified the binding and dropped the indentation. - Removed the useless header files in the drivers. - Used an array lookup instead of a pile of conditions about parent clocks' name. - Added clocks operation on driver remove. v1: https://lore.kernel.org/all/20230120024445.244345-1-xingyu.wu@starfivetech.com/ Emil Renner Berthing (1): clk: starfive: Add StarFive JH7110 System-Top-Group clock driver Xingyu Wu (8): dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator clk: starfive: Add StarFive JH7110 Video-Output clock driver reset: starfive: jh7110: Add StarFive STG/ISP/VOUT resets support riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocks riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG nodes .../clock/starfive,jh7110-ispcrg.yaml | 87 +++++++ .../clock/starfive,jh7110-stgcrg.yaml | 82 ++++++ .../clock/starfive,jh7110-voutcrg.yaml | 90 +++++++ .../jh7110-starfive-visionfive-2.dtsi | 8 + arch/riscv/boot/dts/starfive/jh7110.dtsi | 67 +++++ drivers/clk/starfive/Kconfig | 24 ++ drivers/clk/starfive/Makefile | 3 + .../clk/starfive/clk-starfive-jh7110-isp.c | 232 +++++++++++++++++ .../clk/starfive/clk-starfive-jh7110-stg.c | 173 +++++++++++++ .../clk/starfive/clk-starfive-jh7110-vout.c | 239 ++++++++++++++++++ drivers/clk/starfive/clk-starfive-jh7110.h | 6 + .../reset/starfive/reset-starfive-jh7110.c | 30 +++ .../dt-bindings/clock/starfive,jh7110-crg.h | 74 ++++++ .../dt-bindings/reset/starfive,jh7110-crg.h | 60 +++++ 14 files changed, 1175 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-isp.c create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-stg.c create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-vout.c