| Message ID | 20240108232145.2116455-1-Frank.Li@nxp.com |
|---|---|
| Headers | show |
| Series | PCI: imx6: Clean up and add imx95 pci support | expand |
On Mon, 08 Jan 2024 18:21:44 -0500, Frank Li wrote: > Add i.MX95 PCIe "fsl,imx95-pcie-ep" compatible string. > Add reg-name: "atu", "dbi2", "dma" and "app". > Reuse PCI linux,pci-domain as controller id at endpoint. > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > > Notes: > Change from v1 to v3 > - new patches at v3 > > .../bindings/pci/fsl,imx6q-pcie-ep.yaml | 57 ++++++++++++++++--- > 1 file changed, 49 insertions(+), 8 deletions(-) > Reviewed-by: Rob Herring <robh@kernel.org>
On Mon, Jan 08, 2024 at 06:21:29PM -0500, Frank Li wrote: > first 6 patches use drvdata: flags to simplify some switch-case code. > Improve maintaince and easy to read code. @manivannan: Could you help review these? most of these patch have gotten your review tag. Frank > > Then add imx95 basic pci host function. > > follow two patch do endpoint code clean up. > Then add imx95 basic endpont function. > > Compared with v2, added EP function support and some fixes, please change > notes at each patches. > > dt-binding pass pcie node: > > pcie0: pcie@4c300000 { > compatible = "fsl,imx95-pcie"; > reg = <0 0x4c300000 0 0x40000>, > <0 0x4c360000 0 0x10000>, > <0 0x4c340000 0 0x20000>, > <0 0x60100000 0 0xfe00000>; > reg-names = "dbi", "atu", "app", "config"; > #address-cells = <3>; > #size-cells = <2>; > device_type = "pci"; > linux,pci-domain = <0>; > bus-range = <0x00 0xff>; > ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>, > <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>; > num-lanes = <1>; > num-viewport = <8>; > interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; > interrupt-names = "msi"; > #interrupt-cells = <1>; > interrupt-map-mask = <0 0 0 0x7>; > interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, > <0 0 0 2 &gic 0 0 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, > <0 0 0 3 &gic 0 0 GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, > <0 0 0 4 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; > fsl,max-link-speed = <3>; > clocks = <&scmi_clk IMX95_CLK_HSIO>, > <&scmi_clk IMX95_CLK_HSIOPLL>, > <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, > <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; > clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; > assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, > <&scmi_clk IMX95_CLK_HSIOPLL>, > <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; > assigned-clock-rates = <3600000000>, <100000000>, <10000000>; > assigned-clock-parents = <0>, <0>, > <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; > power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; > /* 0x30~0x37 stream id for pci0 */ > /* > * iommu-map = <0x000 &apps_smmu 0x30 0x1>, > * <0x100 &apps_smmu 0x31 0x1>; > */ > status = "disabled"; > }; > > pcie1: pcie-ep@4c380000 { > compatible = "fsl,imx95-pcie-ep"; > reg = <0 0x4c380000 0 0x20000>, > <0 0x4c3e0000 0 0x1000>, > <0 0x4c3a0000 0 0x1000>, > <0 0x4c3c0000 0 0x10000>, > <0 0x4c3f0000 0 0x10000>, > <0xa 0 1 0>; > reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space"; > interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; > interrupt-names = "dma"; > fsl,max-link-speed = <3>; > clocks = <&scmi_clk IMX95_CLK_HSIO>, > <&scmi_clk IMX95_CLK_HSIOPLL>, > <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, > <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; > clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; > assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, > <&scmi_clk IMX95_CLK_HSIOPLL>, > <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; > assigned-clock-rates = <3600000000>, <100000000>, <10000000>; > assigned-clock-parents = <0>, <0>, > <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; > power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; > status = "disabled"; > }; > > Frank Li (15): > PCI: imx6: Simplify clock handling by using clk_bulk*() function > PCI: imx6: Simplify phy handling by using IMX6_PCIE_FLAG_HAS_PHYDRV > PCI: imx6: Simplify reset handling by using by using > *_FLAG_HAS_*_RESET > dt-bindings: imx6q-pcie: Add linux,pci-domain as required for iMX8MQ > PCI: imx6: Using "linux,pci-domain" as slot ID > PCI: imx6: Simplify ltssm_enable() by using ltssm_off and ltssm_mask > PCI: imx6: Simplify configure_type() by using mode_off and mode_mask > PCI: imx6: Simplify switch-case logic by involve init_phy callback > dt-bindings: imx6q-pcie: Clean up irrationality clocks check > dt-bindings: imx6q-pcie: restruct reg and reg-name > PCI: imx6: Add iMX95 PCIe Root Complex support > PCI: imx6: Clean up get addr_space code > PCI: imx6: Add epc_features in imx6_pcie_drvdata > dt-bindings: imx6q-pcie: Add iMX95 pcie endpoint compatible string > PCI: imx6: Add iMX95 Endpoint (EP) support > > Richard Zhu (1): > dt-bindings: imx6q-pcie: Add imx95 pcie compatible string > > .../bindings/pci/fsl,imx6q-pcie-common.yaml | 28 +- > .../bindings/pci/fsl,imx6q-pcie-ep.yaml | 57 +- > .../bindings/pci/fsl,imx6q-pcie.yaml | 49 +- > drivers/pci/controller/dwc/pci-imx6.c | 643 ++++++++++-------- > 4 files changed, 465 insertions(+), 312 deletions(-) > > -- > 2.34.1 >
On Mon, Jan 08, 2024 at 06:21:36PM -0500, Frank Li wrote: > Add drvdata::mode_off and drvdata::mode_mask to simplify > imx6_pcie_configure_type() logic. > > Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - Mani > --- > > Notes: > Change from v7 to v8 > - replace simple with simplify > - remove reduntant comments about FILED_PREP > Change from v3 to v7 > - none > Change from v2 to v3 > - none > Change from v1 to v2 > - use ffs() to fixe build error. > > Change from v2 to v3 > - none > Change from v1 to v2 > - use ffs() to fixe build error. > > drivers/pci/controller/dwc/pci-imx6.c | 59 ++++++++++++++++++--------- > 1 file changed, 39 insertions(+), 20 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index 818e73157e724..fd83af238fa60 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -68,6 +68,7 @@ enum imx6_pcie_variants { > > #define IMX6_PCIE_MAX_CLKS 6 > > +#define IMX6_PCIE_MAX_INSTANCES 2 > struct imx6_pcie_drvdata { > enum imx6_pcie_variants variant; > enum dw_pcie_device_mode mode; > @@ -78,6 +79,8 @@ struct imx6_pcie_drvdata { > const u32 clks_cnt; > const u32 ltssm_off; > const u32 ltssm_mask; > + const u32 mode_off[IMX6_PCIE_MAX_INSTANCES]; > + const u32 mode_mask[IMX6_PCIE_MAX_INSTANCES]; > }; > > struct imx6_pcie { > @@ -174,32 +177,24 @@ static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie) > > static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) > { > - unsigned int mask, val, mode; > + const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; > + unsigned int mask, val, mode, id; > > - if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE) > + if (drvdata->mode == DW_PCIE_EP_TYPE) > mode = PCI_EXP_TYPE_ENDPOINT; > else > mode = PCI_EXP_TYPE_ROOT_PORT; > > - switch (imx6_pcie->drvdata->variant) { > - case IMX8MQ: > - case IMX8MQ_EP: > - if (imx6_pcie->controller_id == 1) { > - mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE; > - val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, > - mode); > - } else { > - mask = IMX6Q_GPR12_DEVICE_TYPE; > - val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode); > - } > - break; > - default: > - mask = IMX6Q_GPR12_DEVICE_TYPE; > - val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode); > - break; > - } > + id = imx6_pcie->controller_id; > + > + /* If mode_mask[id] is zero, means each controller have its individual gpr */ > + if (!drvdata->mode_mask[id]) > + id = 0; > + > + mask = drvdata->mode_mask[id]; > + val = mode << (ffs(mask) - 1); > > - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val); > + regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val); > } > > static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val) > @@ -1389,6 +1384,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { > .clks_cnt = ARRAY_SIZE(imx6_3clks_bus_pcie_phy), > .ltssm_off = IOMUXC_GPR12, > .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, > + .mode_off[0] = IOMUXC_GPR12, > + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, > }, > [IMX6SX] = { > .variant = IMX6SX, > @@ -1400,6 +1397,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { > .clks_cnt = ARRAY_SIZE(imx6_4clks_bus_pcie_phy_axi), > .ltssm_off = IOMUXC_GPR12, > .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, > + .mode_off[0] = IOMUXC_GPR12, > + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, > }, > [IMX6QP] = { > .variant = IMX6QP, > @@ -1412,6 +1411,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { > .clks_cnt = ARRAY_SIZE(imx6_3clks_bus_pcie_phy), > .ltssm_off = IOMUXC_GPR12, > .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, > + .mode_off[0] = IOMUXC_GPR12, > + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, > }, > [IMX7D] = { > .variant = IMX7D, > @@ -1421,6 +1422,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { > .gpr = "fsl,imx7d-iomuxc-gpr", > .clk_names = imx6_3clks_bus_pcie_phy, > .clks_cnt = ARRAY_SIZE(imx6_3clks_bus_pcie_phy), > + .mode_off[0] = IOMUXC_GPR12, > + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, > }, > [IMX8MQ] = { > .variant = IMX8MQ, > @@ -1429,6 +1432,10 @@ static const struct imx6_pcie_drvdata drvdata[] = { > .gpr = "fsl,imx8mq-iomuxc-gpr", > .clk_names = imx6_4clks_bus_pcie_phy_aux, > .clks_cnt = ARRAY_SIZE(imx6_4clks_bus_pcie_phy_aux), > + .mode_off[0] = IOMUXC_GPR12, > + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, > + .mode_off[1] = IOMUXC_GPR12, > + .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, > }, > [IMX8MM] = { > .variant = IMX8MM, > @@ -1438,6 +1445,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { > .gpr = "fsl,imx8mm-iomuxc-gpr", > .clk_names = imx6_3clks_bus_pcie_aux, > .clks_cnt = ARRAY_SIZE(imx6_3clks_bus_pcie_aux), > + .mode_off[0] = IOMUXC_GPR12, > + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, > }, > [IMX8MP] = { > .variant = IMX8MP, > @@ -1447,6 +1456,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { > .gpr = "fsl,imx8mp-iomuxc-gpr", > .clk_names = imx6_3clks_bus_pcie_aux, > .clks_cnt = ARRAY_SIZE(imx6_3clks_bus_pcie_aux), > + .mode_off[0] = IOMUXC_GPR12, > + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, > }, > [IMX8MQ_EP] = { > .variant = IMX8MQ_EP, > @@ -1456,6 +1467,10 @@ static const struct imx6_pcie_drvdata drvdata[] = { > .gpr = "fsl,imx8mq-iomuxc-gpr", > .clk_names = imx6_4clks_bus_pcie_phy_aux, > .clks_cnt = ARRAY_SIZE(imx6_4clks_bus_pcie_phy_aux), > + .mode_off[0] = IOMUXC_GPR12, > + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, > + .mode_off[1] = IOMUXC_GPR12, > + .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, > }, > [IMX8MM_EP] = { > .variant = IMX8MM_EP, > @@ -1464,6 +1479,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { > .gpr = "fsl,imx8mm-iomuxc-gpr", > .clk_names = imx6_3clks_bus_pcie_aux, > .clks_cnt = ARRAY_SIZE(imx6_3clks_bus_pcie_aux), > + .mode_off[0] = IOMUXC_GPR12, > + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, > }, > [IMX8MP_EP] = { > .variant = IMX8MP_EP, > @@ -1472,6 +1489,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { > .gpr = "fsl,imx8mp-iomuxc-gpr", > .clk_names = imx6_3clks_bus_pcie_aux, > .clks_cnt = ARRAY_SIZE(imx6_3clks_bus_pcie_aux), > + .mode_off[0] = IOMUXC_GPR12, > + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, > }, > }; > > -- > 2.34.1 >
first 6 patches use drvdata: flags to simplify some switch-case code. Improve maintaince and easy to read code. Then add imx95 basic pci host function. follow two patch do endpoint code clean up. Then add imx95 basic endpont function. Compared with v2, added EP function support and some fixes, please change notes at each patches. dt-binding pass pcie node: pcie0: pcie@4c300000 { compatible = "fsl,imx95-pcie"; reg = <0 0x4c300000 0 0x40000>, <0 0x4c360000 0 0x10000>, <0 0x4c340000 0 0x20000>, <0 0x60100000 0 0xfe00000>; reg-names = "dbi", "atu", "app", "config"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; linux,pci-domain = <0>; bus-range = <0x00 0xff>; ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>, <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>; num-lanes = <1>; num-viewport = <8>; interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 2 &gic 0 0 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 3 &gic 0 0 GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, <0 0 0 4 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; fsl,max-link-speed = <3>; clocks = <&scmi_clk IMX95_CLK_HSIO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; assigned-clock-rates = <3600000000>, <100000000>, <10000000>; assigned-clock-parents = <0>, <0>, <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; /* 0x30~0x37 stream id for pci0 */ /* * iommu-map = <0x000 &apps_smmu 0x30 0x1>, * <0x100 &apps_smmu 0x31 0x1>; */ status = "disabled"; }; pcie1: pcie-ep@4c380000 { compatible = "fsl,imx95-pcie-ep"; reg = <0 0x4c380000 0 0x20000>, <0 0x4c3e0000 0 0x1000>, <0 0x4c3a0000 0 0x1000>, <0 0x4c3c0000 0 0x10000>, <0 0x4c3f0000 0 0x10000>, <0xa 0 1 0>; reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space"; interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "dma"; fsl,max-link-speed = <3>; clocks = <&scmi_clk IMX95_CLK_HSIO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; assigned-clock-rates = <3600000000>, <100000000>, <10000000>; assigned-clock-parents = <0>, <0>, <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; status = "disabled"; }; Frank Li (15): PCI: imx6: Simplify clock handling by using clk_bulk*() function PCI: imx6: Simplify phy handling by using IMX6_PCIE_FLAG_HAS_PHYDRV PCI: imx6: Simplify reset handling by using by using *_FLAG_HAS_*_RESET dt-bindings: imx6q-pcie: Add linux,pci-domain as required for iMX8MQ PCI: imx6: Using "linux,pci-domain" as slot ID PCI: imx6: Simplify ltssm_enable() by using ltssm_off and ltssm_mask PCI: imx6: Simplify configure_type() by using mode_off and mode_mask PCI: imx6: Simplify switch-case logic by involve init_phy callback dt-bindings: imx6q-pcie: Clean up irrationality clocks check dt-bindings: imx6q-pcie: restruct reg and reg-name PCI: imx6: Add iMX95 PCIe Root Complex support PCI: imx6: Clean up get addr_space code PCI: imx6: Add epc_features in imx6_pcie_drvdata dt-bindings: imx6q-pcie: Add iMX95 pcie endpoint compatible string PCI: imx6: Add iMX95 Endpoint (EP) support Richard Zhu (1): dt-bindings: imx6q-pcie: Add imx95 pcie compatible string .../bindings/pci/fsl,imx6q-pcie-common.yaml | 28 +- .../bindings/pci/fsl,imx6q-pcie-ep.yaml | 57 +- .../bindings/pci/fsl,imx6q-pcie.yaml | 49 +- drivers/pci/controller/dwc/pci-imx6.c | 643 ++++++++++-------- 4 files changed, 465 insertions(+), 312 deletions(-)