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[209.132.180.67]) by mx.google.com with ESMTP id zk9si5267935pac.144.2014.01.25.08.46.50; Sat, 25 Jan 2014 08:46:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752265AbaAYQqt (ORCPT + 9 others); Sat, 25 Jan 2014 11:46:49 -0500 Received: from tx2ehsobe001.messaging.microsoft.com ([65.55.88.11]:53551 "EHLO tx2outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752161AbaAYQqt convert rfc822-to-8bit (ORCPT ); Sat, 25 Jan 2014 11:46:49 -0500 Received: from mail172-tx2-R.bigfish.com (10.9.14.225) by TX2EHSOBE007.bigfish.com (10.9.40.27) with Microsoft SMTP Server id 14.1.225.22; Sat, 25 Jan 2014 16:46:48 +0000 Received: from mail172-tx2 (localhost [127.0.0.1]) by mail172-tx2-R.bigfish.com (Postfix) with ESMTP id 790C64402B9; Sat, 25 Jan 2014 16:46:48 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 7 X-BigFish: VS7(z3e12hzc89bhb922lc8kzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah21bch1fc6hzz1de098h8275bh8275dh1de097hz2dh87h2a8h839h93fhd24he5bhf0ah1288h12a5h12a9h12bdh137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh2222h224fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h2218h2216h226dh22d0h24afh2327h2336h2438h2461h2487h24d7h1151h1155h) X-FB-DOMAIN-IP-MATCH: fail Received: from mail172-tx2 (localhost.localdomain [127.0.0.1]) by mail172-tx2 (MessageSwitch) id 1390668407123947_9450; Sat, 25 Jan 2014 16:46:47 +0000 (UTC) Received: from TX2EHSMHS014.bigfish.com (unknown [10.9.14.236]) by mail172-tx2.bigfish.com (Postfix) with ESMTP id 151E62005D; Sat, 25 Jan 2014 16:46:47 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by TX2EHSMHS014.bigfish.com (10.9.99.114) with Microsoft SMTP Server (TLS) id 14.16.227.3; Sat, 25 Jan 2014 16:46:41 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server (TLS) id 14.3.158.2; Sat, 25 Jan 2014 16:46:40 +0000 Received: from S2101-09.ap.freescale.net ([10.192.185.238]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s0PGk7uQ013196; Sat, 25 Jan 2014 09:46:37 -0700 From: Shawn Guo To: Rob Herring , CC: , Russell King - ARM Linux , , , Shawn Guo Subject: =?UTF-8?q?=5BPATCH=207/9=5D=20ARM=3A=20dts=3A=20imx25=3A=20remove=20the=20use=20of=20pingrp=20macros?= Date: Sun, 26 Jan 2014 00:43:09 +0800 Message-ID: <1390668191-20289-8-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1390668191-20289-1-git-send-email-shawn.guo@linaro.org> References: <1390668191-20289-1-git-send-email-shawn.guo@linaro.org> MIME-Version: 1.0 X-OriginatorOrg: sigmatel.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: shawn.guo@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.170 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , We created the pingrp macros in imx25-pingrp.h for purpose of less LOC when same pin group is used by multiple boards. However, DT maintainers take it as an abuse of DTC macro support. So let's get rid of it to make the pins used by given device more intuitive. Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi | 17 +++- .../boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts | 56 ++++++++++++-- arch/arm/boot/dts/imx25-pingrp.h | 81 -------------------- arch/arm/boot/dts/imx25.dtsi | 2 +- 4 files changed, 67 insertions(+), 89 deletions(-) delete mode 100644 arch/arm/boot/dts/imx25-pingrp.h diff --git a/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi b/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi index 8abd45a..d6f2764 100644 --- a/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi +++ b/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi @@ -43,11 +43,24 @@ &iomuxc { imx25-eukrea-cpuimx25 { pinctrl_fec: fecgrp { - fsl,pins = ; + fsl,pins = < + MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 + MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0 + MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 + MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 + MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 + MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 + MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 + MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 + MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 + >; }; pinctrl_i2c1: i2c1grp { - fsl,pins = ; + fsl,pins = < + MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000 + MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000 + >; }; }; }; diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts index 30073f8..62fb3da 100644 --- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts +++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts @@ -78,11 +78,23 @@ &iomuxc { imx25-eukrea-mbimxsd25-baseboard { pinctrl_audmux: audmuxgrp { - fsl,pins = ; + fsl,pins = < + MX25_PAD_KPP_COL3__AUD5_TXFS 0xe0 + MX25_PAD_KPP_COL2__AUD5_TXC 0xe0 + MX25_PAD_KPP_COL1__AUD5_RXD 0xe0 + MX25_PAD_KPP_COL0__AUD5_TXD 0xe0 + >; }; pinctrl_esdhc1: esdhc1grp { - fsl,pins = ; + fsl,pins = < + MX25_PAD_SD1_CMD__SD1_CMD 0x400000c0 + MX25_PAD_SD1_CLK__SD1_CLK 0x400000c0 + MX25_PAD_SD1_DATA0__SD1_DATA0 0x400000c0 + MX25_PAD_SD1_DATA1__SD1_DATA1 0x400000c0 + MX25_PAD_SD1_DATA2__SD1_DATA2 0x400000c0 + MX25_PAD_SD1_DATA3__SD1_DATA3 0x400000c0 + >; }; pinctrl_gpiokeys: gpiokeysgrp { @@ -94,15 +106,49 @@ }; pinctrl_lcdc: lcdcgrp { - fsl,pins = ; + fsl,pins = < + MX25_PAD_LD0__LD0 0x1 + MX25_PAD_LD1__LD1 0x1 + MX25_PAD_LD2__LD2 0x1 + MX25_PAD_LD3__LD3 0x1 + MX25_PAD_LD4__LD4 0x1 + MX25_PAD_LD5__LD5 0x1 + MX25_PAD_LD6__LD6 0x1 + MX25_PAD_LD7__LD7 0x1 + MX25_PAD_LD8__LD8 0x1 + MX25_PAD_LD9__LD9 0x1 + MX25_PAD_LD10__LD10 0x1 + MX25_PAD_LD11__LD11 0x1 + MX25_PAD_LD12__LD12 0x1 + MX25_PAD_LD13__LD13 0x1 + MX25_PAD_LD14__LD14 0x1 + MX25_PAD_LD15__LD15 0x1 + MX25_PAD_GPIO_E__LD16 0x1 + MX25_PAD_GPIO_F__LD17 0x1 + MX25_PAD_HSYNC__HSYNC 0x80000000 + MX25_PAD_VSYNC__VSYNC 0x80000000 + MX25_PAD_LSCLK__LSCLK 0x80000000 + MX25_PAD_OE_ACD__OE_ACD 0x80000000 + MX25_PAD_CONTRAST__CONTRAST 0x80000000 + >; }; pinctrl_uart1: uart1grp { - fsl,pins = ; + fsl,pins = < + MX25_PAD_UART1_RTS__UART1_RTS 0xe0 + MX25_PAD_UART1_CTS__UART1_CTS 0xe0 + MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 + MX25_PAD_UART1_RXD__UART1_RXD 0xc0 + >; }; pinctrl_uart2: uart2grp { - fsl,pins = ; + fsl,pins = < + MX25_PAD_UART2_RXD__UART2_RXD 0x80000000 + MX25_PAD_UART2_TXD__UART2_TXD 0x80000000 + MX25_PAD_UART2_RTS__UART2_RTS 0x80000000 + MX25_PAD_UART2_CTS__UART2_CTS 0x80000000 + >; }; }; }; diff --git a/arch/arm/boot/dts/imx25-pingrp.h b/arch/arm/boot/dts/imx25-pingrp.h deleted file mode 100644 index 4a35a63..0000000 --- a/arch/arm/boot/dts/imx25-pingrp.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright 2013 Eukréa Electromatique - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef __DTS_IMX25_PINGRP_H -#define __DTS_IMX25_PINGRP_H - -#include "imx25-pinfunc.h" - -#define MX25_AUDMUX_PINGRP1 \ - MX25_PAD_KPP_COL3__AUD5_TXFS 0xe0 \ - MX25_PAD_KPP_COL2__AUD5_TXC 0xe0 \ - MX25_PAD_KPP_COL1__AUD5_RXD 0xe0 \ - MX25_PAD_KPP_COL0__AUD5_TXD 0xe0 - -#define MX25_ESDHC1_PINGRP1 \ - MX25_PAD_SD1_CMD__SD1_CMD 0x400000c0 \ - MX25_PAD_SD1_CLK__SD1_CLK 0x400000c0 \ - MX25_PAD_SD1_DATA0__SD1_DATA0 0x400000c0 \ - MX25_PAD_SD1_DATA1__SD1_DATA1 0x400000c0 \ - MX25_PAD_SD1_DATA2__SD1_DATA2 0x400000c0 \ - MX25_PAD_SD1_DATA3__SD1_DATA3 0x400000c0 - -#define MX25_FEC_PINGRP1 \ - MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 \ - MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0 \ - MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 \ - MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 \ - MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 \ - MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 \ - MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 \ - MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 \ - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x1c0 - -#define MX25_I2C1_PINGRP1 \ - MX25_PAD_I2C1_CLK__I2C1_CLK 0x80000000 \ - MX25_PAD_I2C1_DAT__I2C1_DAT 0x80000000 - -#define MX25_LCDC_PINGRP1 \ - MX25_PAD_LD0__LD0 0x1 \ - MX25_PAD_LD1__LD1 0x1 \ - MX25_PAD_LD2__LD2 0x1 \ - MX25_PAD_LD3__LD3 0x1 \ - MX25_PAD_LD4__LD4 0x1 \ - MX25_PAD_LD5__LD5 0x1 \ - MX25_PAD_LD6__LD6 0x1 \ - MX25_PAD_LD7__LD7 0x1 \ - MX25_PAD_LD8__LD8 0x1 \ - MX25_PAD_LD9__LD9 0x1 \ - MX25_PAD_LD10__LD10 0x1 \ - MX25_PAD_LD11__LD11 0x1 \ - MX25_PAD_LD12__LD12 0x1 \ - MX25_PAD_LD13__LD13 0x1 \ - MX25_PAD_LD14__LD14 0x1 \ - MX25_PAD_LD15__LD15 0x1 \ - MX25_PAD_GPIO_E__LD16 0x1 \ - MX25_PAD_GPIO_F__LD17 0x1 \ - MX25_PAD_HSYNC__HSYNC 0x80000000 \ - MX25_PAD_VSYNC__VSYNC 0x80000000 \ - MX25_PAD_LSCLK__LSCLK 0x80000000 \ - MX25_PAD_OE_ACD__OE_ACD 0x80000000 \ - MX25_PAD_CONTRAST__CONTRAST 0x80000000 - -#define MX25_UART1_PINGRP1 \ - MX25_PAD_UART1_RTS__UART1_RTS 0xe0 \ - MX25_PAD_UART1_CTS__UART1_CTS 0xe0 \ - MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 \ - MX25_PAD_UART1_RXD__UART1_RXD 0xc0 - -#define MX25_UART2_PINGRP1 \ - MX25_PAD_UART2_RXD__UART2_RXD 0x80000000 \ - MX25_PAD_UART2_TXD__UART2_TXD 0x80000000 \ - MX25_PAD_UART2_RTS__UART2_RTS 0x80000000 \ - MX25_PAD_UART2_CTS__UART2_CTS 0x80000000 - -#endif /* __DTS_IMX25_PINGRP_H */ diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index 9e9e3b8..32f760e 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -10,7 +10,7 @@ */ #include "skeleton.dtsi" -#include "imx25-pingrp.h" +#include "imx25-pinfunc.h" / { aliases {