From patchwork Tue Sep 9 20:17:15 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Murali Karicheri X-Patchwork-Id: 37150 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-oi0-f71.google.com (mail-oi0-f71.google.com [209.85.218.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 5CD1420566 for ; Tue, 9 Sep 2014 20:17:35 +0000 (UTC) Received: by mail-oi0-f71.google.com with SMTP id e131sf27945637oig.2 for ; Tue, 09 Sep 2014 13:17:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe:content-type; bh=P/6U7n6AhLqeFygyyUO7sTZDJfQVbhoqVsI4z4WX1w8=; b=jAI7sngQTRgs/flSWtvEmQ4bEU1Zokd5cFcFGiWWrQnvNflmnyx+jjAMbJwRiTuXgH QmmjxIb5NqXhcxzZ9NbjjwRYG8KE9wUUR8Swg0PNNq+kPPlTlLVkLfZU+kOJejwavTjD z3u6pMHXwvOENcPgknwBKS4Sx1UwNq8nVts1FUJyrYbXzqBCvxDRYGFf+gTnuHIP386h YNu0mjUv+1FyEs95sbNuOR+ZPI0gEclyZqflQmMCEpMD27l2DH3h7EqVph+xxMtbEFeA p4R7b5Du0kAR/+QpfF9glHAVlXtIN2u1WCswJYJIEnFgYtlYlMitkZVq82VtxX/Q1vkT tU7w== X-Gm-Message-State: ALoCoQnoyDd/UiPgRrRgsjOMQXA2rCKF7Us6kAjYEAlSIzIk/9o8HVCgioMvDrf1w6jWGgzlKqVz X-Received: by 10.182.91.43 with SMTP id cb11mr24025843obb.13.1410293854957; Tue, 09 Sep 2014 13:17:34 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.25.176 with SMTP id 45ls295563qgt.86.gmail; Tue, 09 Sep 2014 13:17:34 -0700 (PDT) X-Received: by 10.52.162.74 with SMTP id xy10mr6405647vdb.51.1410293854803; Tue, 09 Sep 2014 13:17:34 -0700 (PDT) Received: from mail-vc0-f172.google.com (mail-vc0-f172.google.com [209.85.220.172]) by mx.google.com with ESMTPS id re1si5605268vcb.6.2014.09.09.13.17.34 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 09 Sep 2014 13:17:34 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.172 as permitted sender) client-ip=209.85.220.172; Received: by mail-vc0-f172.google.com with SMTP id hy10so3894866vcb.17 for ; Tue, 09 Sep 2014 13:17:34 -0700 (PDT) X-Received: by 10.221.9.1 with SMTP id ou1mr2798659vcb.60.1410293854711; Tue, 09 Sep 2014 13:17:34 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.221.45.67 with SMTP id uj3csp337903vcb; Tue, 9 Sep 2014 13:17:34 -0700 (PDT) X-Received: by 10.70.14.67 with SMTP id n3mr6966053pdc.132.1410293853466; Tue, 09 Sep 2014 13:17:33 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ur1si24872716pac.131.2014.09.09.13.17.32 for ; Tue, 09 Sep 2014 13:17:33 -0700 (PDT) Received-SPF: none (google.com: devicetree-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752380AbaIIURb (ORCPT + 5 others); Tue, 9 Sep 2014 16:17:31 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:51782 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752373AbaIIURb (ORCPT ); Tue, 9 Sep 2014 16:17:31 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s89KGuZq005627; Tue, 9 Sep 2014 15:16:56 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s89KGuql015432; Tue, 9 Sep 2014 15:16:56 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Tue, 9 Sep 2014 15:16:56 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s89KGsvh010696; Tue, 9 Sep 2014 15:16:55 -0500 From: Murali Karicheri To: , , , , , , , , , CC: Murali Karicheri Subject: [PATCH v2 2/2] PCI: keystone: update to support multiple pci ports Date: Tue, 9 Sep 2014 16:17:15 -0400 Message-ID: <1410293835-13050-2-git-send-email-m-karicheri2@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1410293835-13050-1-git-send-email-m-karicheri2@ti.com> References: <1410293835-13050-1-git-send-email-m-karicheri2@ti.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: m-karicheri2@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.172 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , K2E SoC has two PCI ports. The SATA controller is connected to second PCI port (port 1). This patch enhances the driver to support multiple ports. Update the DT Documentation for the new attribute, ti,pcie-port and remove the note for bootargs as this is no longer needed. Signed-off-by: Murali Karicheri --- - updated based on comment against v1 .../devicetree/bindings/pci/pci-keystone.txt | 8 +++++--- drivers/pci/host/pci-keystone.c | 15 ++++++++++----- drivers/pci/host/pci-keystone.h | 4 ++-- 3 files changed, 17 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt index bedacf0..c8f5773 100644 --- a/Documentation/devicetree/bindings/pci/pci-keystone.txt +++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt @@ -56,11 +56,13 @@ Optional properties:- phy-names: name of the Generic Keystine SerDes phy for PCI - If boot loader already does PCI link establishment, then phys and phy-names shouldn't be present. + ti,pcie-port: PCI port number. This is used to configure the PCI port + number. For example K2E SoC supports 2 PCI ports and PCI bindings + for the second port adds ti,pcie-port = <1> to identify second port + and driver uses this to configure the PCI mode register for second + port. If not present, port number 0 is assumed. Designware DT Properties not applicable for Keystone PCI 1. pcie_bus clock-names not used. Instead, a phandle to phys is used. -Note for PCI driver usage -========================= -Driver requires pci=pcie_bus_perf in the bootargs for proper functioning. diff --git a/drivers/pci/host/pci-keystone.c b/drivers/pci/host/pci-keystone.c index f1119eb..893820d 100644 --- a/drivers/pci/host/pci-keystone.c +++ b/drivers/pci/host/pci-keystone.c @@ -253,8 +253,8 @@ static int keystone_pcie_fault(unsigned long addr, unsigned int fsr, static void __init ks_pcie_host_init(struct pcie_port *pp) { - u32 vendor_device_id, val; struct keystone_pcie *ks_pcie = to_keystone_pcie(pp); + u32 val; ks_pcie_establish_link(ks_pcie); ks_dw_pcie_setup_rc_app_regs(ks_pcie); @@ -263,8 +263,7 @@ static void __init ks_pcie_host_init(struct pcie_port *pp) pp->dbi_base + PCI_IO_BASE); /* update the Vendor ID */ - vendor_device_id = readl(ks_pcie->va_reg_pciid); - writew((vendor_device_id >> 16), pp->dbi_base + PCI_DEVICE_ID); + writew(ks_pcie->device_id, pp->dbi_base + PCI_DEVICE_ID); /* update the DEV_STAT_CTRL to publish right mrrs */ val = readl(pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL); @@ -345,12 +344,13 @@ static int __exit ks_pcie_remove(struct platform_device *pdev) static int __init ks_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; struct keystone_pcie *ks_pcie; + int ret = 0, port_id = 0; struct pcie_port *pp; struct resource *res; void __iomem *reg_p; struct phy *phy; - int ret = 0; ks_pcie = devm_kzalloc(&pdev->dev, sizeof(*ks_pcie), GFP_KERNEL); @@ -360,6 +360,9 @@ static int __init ks_pcie_probe(struct platform_device *pdev) } pp = &ks_pcie->pp; + /* read the PCI port id */ + of_property_read_u32(np, "ti,pcie-port", &port_id); + /* initialize SerDes Phy if present */ phy = devm_phy_get(dev, "pcie-phy"); if (!IS_ERR_OR_NULL(phy)) { @@ -373,7 +376,9 @@ static int __init ks_pcie_probe(struct platform_device *pdev) reg_p = devm_ioremap_resource(dev, res); if (IS_ERR(reg_p)) return PTR_ERR(reg_p); - ks_pcie->va_reg_pciid = reg_p; + ks_pcie->device_id = readl(reg_p) >> 16; + devm_iounmap(dev, reg_p); + devm_release_mem_region(dev, res->start, resource_size(res)); pp->dev = dev; platform_set_drvdata(pdev, ks_pcie); diff --git a/drivers/pci/host/pci-keystone.h b/drivers/pci/host/pci-keystone.h index 729ea7d..80cfa8e 100644 --- a/drivers/pci/host/pci-keystone.h +++ b/drivers/pci/host/pci-keystone.h @@ -19,8 +19,8 @@ struct keystone_pcie { struct clk *clk; struct pcie_port pp; - void __iomem *va_reg_pciid; - + /* PCI Device ID */ + u32 device_id; int num_legacy_host_irqs; int legacy_host_irqs[MAX_LEGACY_HOST_IRQS]; struct device_node *legacy_intc_np;