From patchwork Fri Oct 2 22:57:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Mason X-Patchwork-Id: 54466 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-lb0-f200.google.com (mail-lb0-f200.google.com [209.85.217.200]) by patches.linaro.org (Postfix) with ESMTPS id 13521218EF for ; Fri, 2 Oct 2015 22:58:59 +0000 (UTC) Received: by lbcao8 with SMTP id ao8sf20852079lbc.1 for ; Fri, 02 Oct 2015 15:58:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-type:sender:precedence :list-id:x-original-sender:x-original-authentication-results :mailing-list:list-post:list-help:list-archive:list-unsubscribe; bh=2lGtBxkOZbcZ4cSS6eIdLwiC94+mtcZKuIsgkGriiTs=; b=SgQHNBEbfQqpRM2dLkf33yB5eSMbBbIWfcr1IFLWArHRt8EKvPuCu7KStaU71u5kAC AiYYVA8AznvKMhIEnubOChRqKYHSqDRT1g3ARQzOBszp1+suKCzFFgVdpngldfrg4qjK XlY2eSQN/859hUjJ13tLBvhHWsY8itBifMEcex1yGJnE6bPKD6+mij1+ZX6apO43OVPw cDnJZk2LZvOuIJEObLmjineKfuNFxhZ6qIgSQtcRBUgGV9CBbxfUPInfXwCwwgu26LET 07JJqRusbjqGzWHxLbVBpkTYhh7Uswd2shJYVSxyhCqAK5+wsyIRDY1rg2CQ8++ehcJG g7Zg== X-Gm-Message-State: ALoCoQnV+q3eT6nCIUULDwCegZtQ028d370LceMPRlFTflMxmDUiRK/LmincQZN/a9bZYFtCE+o+ X-Received: by 10.112.198.33 with SMTP id iz1mr3056764lbc.8.1443826737811; Fri, 02 Oct 2015 15:58:57 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.25.141.198 with SMTP id p189ls296123lfd.79.gmail; Fri, 02 Oct 2015 15:58:57 -0700 (PDT) X-Received: by 10.112.209.4 with SMTP id mi4mr6866592lbc.7.1443826737444; Fri, 02 Oct 2015 15:58:57 -0700 (PDT) Received: from mail-lb0-f171.google.com (mail-lb0-f171.google.com. [209.85.217.171]) by mx.google.com with ESMTPS id d2si7666778lbc.149.2015.10.02.15.58.57 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 02 Oct 2015 15:58:57 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.171 as permitted sender) client-ip=209.85.217.171; Received: by lbbmp1 with SMTP id mp1so33864995lbb.1 for ; Fri, 02 Oct 2015 15:58:57 -0700 (PDT) X-Received: by 10.112.205.138 with SMTP id lg10mr4677785lbc.74.1443826736987; Fri, 02 Oct 2015 15:58:56 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.130.202 with SMTP id og10csp1100lbb; Fri, 2 Oct 2015 15:58:55 -0700 (PDT) X-Received: by 10.68.95.225 with SMTP id dn1mr21621185pbb.11.1443826734937; Fri, 02 Oct 2015 15:58:54 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id tv2si19926641pac.119.2015.10.02.15.58.54; Fri, 02 Oct 2015 15:58:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752017AbbJBW6A (ORCPT + 30 others); Fri, 2 Oct 2015 18:58:00 -0400 Received: from mail-gw2-out.broadcom.com ([216.31.210.63]:37462 "EHLO mail-gw2-out.broadcom.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751863AbbJBW55 (ORCPT ); Fri, 2 Oct 2015 18:57:57 -0400 X-IronPort-AV: E=Sophos;i="5.17,625,1437462000"; d="scan'208";a="76676237" Received: from irvexchcas06.broadcom.com (HELO IRVEXCHCAS06.corp.ad.broadcom.com) ([10.9.208.53]) by mail-gw2-out.broadcom.com with ESMTP; 02 Oct 2015 16:25:11 -0700 Received: from IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) by IRVEXCHCAS06.corp.ad.broadcom.com (10.9.208.53) with Microsoft SMTP Server (TLS) id 14.3.235.1; Fri, 2 Oct 2015 15:57:57 -0700 Received: from mail-irva-13.broadcom.com (10.10.10.20) by IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) with Microsoft SMTP Server id 14.3.235.1; Fri, 2 Oct 2015 15:57:56 -0700 Received: from venom.rtp.broadcom.com (unknown [10.27.64.103]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id DAC0940FE8; Fri, 2 Oct 2015 15:55:07 -0700 (PDT) From: Jon Mason To: Michael Turquette , Stephen Boyd CC: Florian Fainelli , Hauke Mehrtens , Ray Jui , Scott Branden , , , , , Subject: [PATCH 06/10] clk: iproc: Split off dig_filter Date: Fri, 2 Oct 2015 18:57:41 -0400 Message-ID: <1443826665-17570-7-git-send-email-jonmason@broadcom.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1443826665-17570-1-git-send-email-jonmason@broadcom.com> References: <1443826665-17570-1-git-send-email-jonmason@broadcom.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: jonmason@broadcom.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.171 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The PLL loop filter/gain can be located in a separate register on some SoCs. Split these off into a separate variable, so that an offset can be added if necessary. Also, make the necessary modifications to the Cygnus and NSP drivers for this change. Signed-off-by: Jon Mason --- drivers/clk/bcm/clk-cygnus.c | 17 +++++++++++------ drivers/clk/bcm/clk-iproc-pll.c | 14 +++++++++----- drivers/clk/bcm/clk-iproc.h | 10 +++++++++- drivers/clk/bcm/clk-nsp.c | 14 +++++++++----- 4 files changed, 38 insertions(+), 17 deletions(-) diff --git a/drivers/clk/bcm/clk-cygnus.c b/drivers/clk/bcm/clk-cygnus.c index 316c603..c526143 100644 --- a/drivers/clk/bcm/clk-cygnus.c +++ b/drivers/clk/bcm/clk-cygnus.c @@ -34,9 +34,11 @@ { .offset = o, .en_shift = es, .high_shift = hs, \ .high_width = hw, .low_shift = ls, .low_width = lw } -#define reset_val(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \ - .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \ - .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ +#define reset_val(o, rs, prs) { .offset = o, .reset_shift = rs, \ + .p_reset_shift = prs } + +#define df_val(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\ + .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ .ka_width = kaw } #define vco_ctrl_val(uo, lo) { .u_offset = uo, .l_offset = lo } @@ -56,7 +58,8 @@ static const struct iproc_pll_ctrl genpll = { .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_PLL_NEEDS_SW_CFG, .aon = aon_val(0x0, 2, 1, 0), - .reset = reset_val(0x0, 11, 10, 4, 3, 0, 4, 7, 3), + .reset = reset_val(0x0, 11, 10), + .dig_filter = df_val(0x0, 4, 3, 0, 4, 7, 3), .sw_ctrl = sw_ctrl_val(0x10, 31), .ndiv_int = reg_val(0x10, 20, 10), .ndiv_frac = reg_val(0x10, 0, 20), @@ -114,7 +117,8 @@ CLK_OF_DECLARE(cygnus_genpll, "brcm,cygnus-genpll", cygnus_genpll_clk_init); static const struct iproc_pll_ctrl lcpll0 = { .flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG, .aon = aon_val(0x0, 2, 5, 4), - .reset = reset_val(0x0, 31, 30, 27, 3, 23, 4, 19, 4), + .reset = reset_val(0x0, 31, 30), + .dig_filter = df_val(0x0, 27, 3, 23, 4, 19, 4), .sw_ctrl = sw_ctrl_val(0x4, 31), .ndiv_int = reg_val(0x4, 16, 10), .pdiv = reg_val(0x4, 26, 4), @@ -191,7 +195,8 @@ static const struct iproc_pll_ctrl mipipll = { IPROC_CLK_NEEDS_READ_BACK, .aon = aon_val(0x0, 4, 17, 16), .asiu = asiu_gate_val(0x0, 3), - .reset = reset_val(0x0, 11, 10, 4, 3, 0, 4, 7, 4), + .reset = reset_val(0x0, 11, 10), + .dig_filter = df_val(0x0, 4, 3, 0, 4, 7, 4), .ndiv_int = reg_val(0x10, 20, 10), .ndiv_frac = reg_val(0x10, 0, 20), .pdiv = reg_val(0x14, 0, 4), diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-iproc-pll.c index a4602aa..882aced 100644 --- a/drivers/clk/bcm/clk-iproc-pll.c +++ b/drivers/clk/bcm/clk-iproc-pll.c @@ -224,13 +224,17 @@ static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp, u32 val; const struct iproc_pll_ctrl *ctrl = pll->ctrl; const struct iproc_pll_reset_ctrl *reset = &ctrl->reset; + const struct iproc_pll_dig_filter_ctrl *dig_filter = &ctrl->dig_filter; + + val = readl(pll->pll_base + dig_filter->offset); + val &= ~(bit_mask(dig_filter->ki_width) << dig_filter->ki_shift | + bit_mask(dig_filter->kp_width) << dig_filter->kp_shift | + bit_mask(dig_filter->ka_width) << dig_filter->ka_shift); + val |= ki << dig_filter->ki_shift | kp << dig_filter->kp_shift | + ka << dig_filter->ka_shift; + iproc_pll_write(pll, pll->pll_base, dig_filter->offset, val); val = readl(pll->pll_base + reset->offset); - val &= ~(bit_mask(reset->ki_width) << reset->ki_shift | - bit_mask(reset->kp_width) << reset->kp_shift | - bit_mask(reset->ka_width) << reset->ka_shift); - val |= ki << reset->ki_shift | kp << reset->kp_shift | - ka << reset->ka_shift; val |= 1 << reset->reset_shift | 1 << reset->p_reset_shift; iproc_pll_write(pll, pll->pll_base, reset->offset, val); } diff --git a/drivers/clk/bcm/clk-iproc.h b/drivers/clk/bcm/clk-iproc.h index ff7bfad..b71c197 100644 --- a/drivers/clk/bcm/clk-iproc.h +++ b/drivers/clk/bcm/clk-iproc.h @@ -94,12 +94,19 @@ struct iproc_pll_aon_pwr_ctrl { }; /* - * Control of the PLL reset, with Ki, Kp, and Ka parameters + * Control of the PLL reset */ struct iproc_pll_reset_ctrl { unsigned int offset; unsigned int reset_shift; unsigned int p_reset_shift; +}; + +/* + * Control of the Ki, Kp, and Ka parameters + */ +struct iproc_pll_dig_filter_ctrl { + unsigned int offset; unsigned int ki_shift; unsigned int ki_width; unsigned int kp_shift; @@ -129,6 +136,7 @@ struct iproc_pll_ctrl { struct iproc_pll_aon_pwr_ctrl aon; struct iproc_asiu_gate asiu; struct iproc_pll_reset_ctrl reset; + struct iproc_pll_dig_filter_ctrl dig_filter; struct iproc_pll_sw_ctrl sw_ctrl; struct iproc_clk_reg_op ndiv_int; struct iproc_clk_reg_op ndiv_frac; diff --git a/drivers/clk/bcm/clk-nsp.c b/drivers/clk/bcm/clk-nsp.c index 708961a..4fc4b1d 100644 --- a/drivers/clk/bcm/clk-nsp.c +++ b/drivers/clk/bcm/clk-nsp.c @@ -28,9 +28,11 @@ #define aon_val(o, pw, ps, is) { .offset = o, .pwr_width = pw, \ .pwr_shift = ps, .iso_shift = is } -#define reset_val(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \ - .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \ - .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ +#define reset_val(o, rs, prs) { .offset = o, .reset_shift = rs, \ + .p_reset_shift = prs } + +#define df_val(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\ + .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ .ka_width = kaw } #define vco_ctrl_val(uo, lo) { .u_offset = uo, .l_offset = lo } @@ -47,7 +49,8 @@ CLK_OF_DECLARE(nsp_armpll, "brcm,nsp-armpll", nsp_armpll_init); static const struct iproc_pll_ctrl genpll = { .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL, .aon = aon_val(0x0, 1, 12, 0), - .reset = reset_val(0x0, 11, 10, 4, 3, 0, 4, 7, 3), + .reset = reset_val(0x0, 11, 10), + .dig_filter = df_val(0x0, 4, 3, 0, 4, 7, 3), .ndiv_int = reg_val(0x14, 20, 10), .ndiv_frac = reg_val(0x14, 0, 20), .pdiv = reg_val(0x18, 24, 3), @@ -103,7 +106,8 @@ CLK_OF_DECLARE(nsp_genpll_clk, "brcm,nsp-genpll", nsp_genpll_clk_init); static const struct iproc_pll_ctrl lcpll0 = { .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL, .aon = aon_val(0x0, 1, 24, 0), - .reset = reset_val(0x0, 23, 22, 16, 3, 12, 4, 19, 4), + .reset = reset_val(0x0, 23, 22), + .dig_filter = df_val(0x0, 16, 3, 12, 4, 19, 4), .ndiv_int = reg_val(0x4, 20, 8), .ndiv_frac = reg_val(0x4, 0, 20), .pdiv = reg_val(0x4, 28, 3),