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[2001:1868:205::9]) by mx.google.com with ESMTPS id la1si7644478pbc.208.2015.10.13.14.10.11 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 13 Oct 2015 14:10:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Zm6oo-0006e8-DO; Tue, 13 Oct 2015 21:09:10 +0000 Received: from mail-gw2-out.broadcom.com ([216.31.210.63]) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Zm6oK-0006Az-4M for linux-arm-kernel@lists.infradead.org; Tue, 13 Oct 2015 21:08:41 +0000 X-IronPort-AV: E=Sophos;i="5.17,680,1437462000"; d="scan'208";a="77549798" Received: from irvexchcas07.broadcom.com (HELO IRVEXCHCAS07.corp.ad.broadcom.com) ([10.9.208.55]) by mail-gw2-out.broadcom.com with ESMTP; 13 Oct 2015 14:36:58 -0700 Received: from IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) by IRVEXCHCAS07.corp.ad.broadcom.com (10.9.208.55) with Microsoft SMTP Server (TLS) id 14.3.235.1; Tue, 13 Oct 2015 14:08:21 -0700 Received: from mail-irva-13.broadcom.com (10.10.10.20) by IRVEXCHSMTP2.corp.ad.broadcom.com (10.9.207.52) with Microsoft SMTP Server id 14.3.235.1; Tue, 13 Oct 2015 14:08:21 -0700 Received: from venom.rtp.broadcom.com (unknown [10.27.64.103]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 242BB40FE6; Tue, 13 Oct 2015 14:05:27 -0700 (PDT) From: Jon Mason To: Michael Turquette , Stephen Boyd Subject: [PATCH v2 5/7] clk: iproc: Split off dig_filter Date: Tue, 13 Oct 2015 17:08:03 -0400 Message-ID: <1444770485-11210-6-git-send-email-jonmason@broadcom.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1444770485-11210-1-git-send-email-jonmason@broadcom.com> References: <1444770485-11210-1-git-send-email-jonmason@broadcom.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20151013_140840_361245_1C917B05 X-CRM114-Status: GOOD ( 11.88 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [216.31.210.63 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H4 RBL: Very Good reputation (+4) [216.31.210.63 listed in wl.mailspike.net] -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Cc: devicetree@vger.kernel.org, Florian Fainelli , Scott Branden , Hauke Mehrtens , linux-kernel@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, Ray Jui , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: jonmason@broadcom.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.52 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 The PLL loop filter/gain can be located in a separate register on some SoCs. Split these off into a separate variable, so that an offset can be added if necessary. Also, make the necessary modifications to the Cygnus and NSP drivers for this change. Signed-off-by: Jon Mason --- drivers/clk/bcm/clk-cygnus.c | 17 +++++++++++------ drivers/clk/bcm/clk-iproc-pll.c | 14 +++++++++----- drivers/clk/bcm/clk-iproc.h | 10 +++++++++- drivers/clk/bcm/clk-nsp.c | 14 +++++++++----- 4 files changed, 38 insertions(+), 17 deletions(-) diff --git a/drivers/clk/bcm/clk-cygnus.c b/drivers/clk/bcm/clk-cygnus.c index aac82c6..3a228b6 100644 --- a/drivers/clk/bcm/clk-cygnus.c +++ b/drivers/clk/bcm/clk-cygnus.c @@ -34,9 +34,11 @@ { .offset = o, .en_shift = es, .high_shift = hs, \ .high_width = hw, .low_shift = ls, .low_width = lw } -#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \ - .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \ - .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ +#define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \ + .p_reset_shift = prs } + +#define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\ + .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ .ka_width = kaw } #define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo } @@ -56,7 +58,8 @@ static const struct iproc_pll_ctrl genpll = { .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_PLL_NEEDS_SW_CFG, .aon = AON_VAL(0x0, 2, 1, 0), - .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3), + .reset = RESET_VAL(0x0, 11, 10), + .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3), .sw_ctrl = SW_CTRL_VAL(0x10, 31), .ndiv_int = REG_VAL(0x10, 20, 10), .ndiv_frac = REG_VAL(0x10, 0, 20), @@ -114,7 +117,8 @@ CLK_OF_DECLARE(cygnus_genpll, "brcm,cygnus-genpll", cygnus_genpll_clk_init); static const struct iproc_pll_ctrl lcpll0 = { .flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG, .aon = AON_VAL(0x0, 2, 5, 4), - .reset = RESET_VAL(0x0, 31, 30, 27, 3, 23, 4, 19, 4), + .reset = RESET_VAL(0x0, 31, 30), + .dig_filter = DF_VAL(0x0, 27, 3, 23, 4, 19, 4), .sw_ctrl = SW_CTRL_VAL(0x4, 31), .ndiv_int = REG_VAL(0x4, 16, 10), .pdiv = REG_VAL(0x4, 26, 4), @@ -191,7 +195,8 @@ static const struct iproc_pll_ctrl mipipll = { IPROC_CLK_NEEDS_READ_BACK, .aon = AON_VAL(0x0, 4, 17, 16), .asiu = ASIU_GATE_VAL(0x0, 3), - .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 4), + .reset = RESET_VAL(0x0, 11, 10), + .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 4), .ndiv_int = REG_VAL(0x10, 20, 10), .ndiv_frac = REG_VAL(0x10, 0, 20), .pdiv = REG_VAL(0x14, 0, 4), diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-iproc-pll.c index 74cdd66..d4aab4e 100644 --- a/drivers/clk/bcm/clk-iproc-pll.c +++ b/drivers/clk/bcm/clk-iproc-pll.c @@ -224,13 +224,17 @@ static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp, u32 val; const struct iproc_pll_ctrl *ctrl = pll->ctrl; const struct iproc_pll_reset_ctrl *reset = &ctrl->reset; + const struct iproc_pll_dig_filter_ctrl *dig_filter = &ctrl->dig_filter; + + val = readl(pll->pll_base + dig_filter->offset); + val &= ~(bit_mask(dig_filter->ki_width) << dig_filter->ki_shift | + bit_mask(dig_filter->kp_width) << dig_filter->kp_shift | + bit_mask(dig_filter->ka_width) << dig_filter->ka_shift); + val |= ki << dig_filter->ki_shift | kp << dig_filter->kp_shift | + ka << dig_filter->ka_shift; + iproc_pll_write(pll, pll->pll_base, dig_filter->offset, val); val = readl(pll->pll_base + reset->offset); - val &= ~(bit_mask(reset->ki_width) << reset->ki_shift | - bit_mask(reset->kp_width) << reset->kp_shift | - bit_mask(reset->ka_width) << reset->ka_shift); - val |= ki << reset->ki_shift | kp << reset->kp_shift | - ka << reset->ka_shift; val |= 1 << reset->reset_shift | 1 << reset->p_reset_shift; iproc_pll_write(pll, pll->pll_base, reset->offset, val); } diff --git a/drivers/clk/bcm/clk-iproc.h b/drivers/clk/bcm/clk-iproc.h index ff7bfad..b71c197 100644 --- a/drivers/clk/bcm/clk-iproc.h +++ b/drivers/clk/bcm/clk-iproc.h @@ -94,12 +94,19 @@ struct iproc_pll_aon_pwr_ctrl { }; /* - * Control of the PLL reset, with Ki, Kp, and Ka parameters + * Control of the PLL reset */ struct iproc_pll_reset_ctrl { unsigned int offset; unsigned int reset_shift; unsigned int p_reset_shift; +}; + +/* + * Control of the Ki, Kp, and Ka parameters + */ +struct iproc_pll_dig_filter_ctrl { + unsigned int offset; unsigned int ki_shift; unsigned int ki_width; unsigned int kp_shift; @@ -129,6 +136,7 @@ struct iproc_pll_ctrl { struct iproc_pll_aon_pwr_ctrl aon; struct iproc_asiu_gate asiu; struct iproc_pll_reset_ctrl reset; + struct iproc_pll_dig_filter_ctrl dig_filter; struct iproc_pll_sw_ctrl sw_ctrl; struct iproc_clk_reg_op ndiv_int; struct iproc_clk_reg_op ndiv_frac; diff --git a/drivers/clk/bcm/clk-nsp.c b/drivers/clk/bcm/clk-nsp.c index bc8ebdcd..cf66f64 100644 --- a/drivers/clk/bcm/clk-nsp.c +++ b/drivers/clk/bcm/clk-nsp.c @@ -26,9 +26,11 @@ #define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \ .pwr_shift = ps, .iso_shift = is } -#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \ - .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \ - .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ +#define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \ + .p_reset_shift = prs } + +#define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\ + .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ .ka_width = kaw } #define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \ @@ -43,7 +45,8 @@ CLK_OF_DECLARE(nsp_armpll, "brcm,nsp-armpll", nsp_armpll_init); static const struct iproc_pll_ctrl genpll = { .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL, .aon = AON_VAL(0x0, 1, 12, 0), - .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3), + .reset = RESET_VAL(0x0, 11, 10), + .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3), .ndiv_int = REG_VAL(0x14, 20, 10), .ndiv_frac = REG_VAL(0x14, 0, 20), .pdiv = REG_VAL(0x18, 24, 3), @@ -99,7 +102,8 @@ CLK_OF_DECLARE(nsp_genpll_clk, "brcm,nsp-genpll", nsp_genpll_clk_init); static const struct iproc_pll_ctrl lcpll0 = { .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL, .aon = AON_VAL(0x0, 1, 24, 0), - .reset = RESET_VAL(0x0, 23, 22, 16, 3, 12, 4, 19, 4), + .reset = RESET_VAL(0x0, 23, 22), + .dig_filter = DF_VAL(0x0, 16, 3, 12, 4, 19, 4), .ndiv_int = REG_VAL(0x4, 20, 8), .ndiv_frac = REG_VAL(0x4, 0, 20), .pdiv = REG_VAL(0x4, 28, 3),