From patchwork Tue Dec 1 09:14:58 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanimir Varbanov X-Patchwork-Id: 57480 Delivered-To: patch@linaro.org Received: by 10.112.155.196 with SMTP id vy4csp2040579lbb; Tue, 1 Dec 2015 01:16:56 -0800 (PST) X-Received: by 10.66.122.39 with SMTP id lp7mr98752879pab.74.1448961416395; Tue, 01 Dec 2015 01:16:56 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id tp10si15727348pac.173.2015.12.01.01.16.56; Tue, 01 Dec 2015 01:16:56 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dkim=neutral (body hash did not verify) header.i=@linaro-org.20150623.gappssmtp.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755882AbbLAJQy (ORCPT + 6 others); Tue, 1 Dec 2015 04:16:54 -0500 Received: from mail-wm0-f45.google.com ([74.125.82.45]:35464 "EHLO mail-wm0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755679AbbLAJQH (ORCPT ); Tue, 1 Dec 2015 04:16:07 -0500 Received: by wmuu63 with SMTP id u63so163930464wmu.0 for ; Tue, 01 Dec 2015 01:16:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Nsv7MXVJh2dkGGF11w8uAFVC23CCxgk5LEXEzrK4iec=; b=Qiwv7mMhBgh+63Lgu8NKUKK7XQQfh+NEHgpE2fS79/RRMOkaecldV+XsZjtdDrZaFx SdVAaw0v6WKMhg4bmOqMZIsCKU+iWvgzttEfjAFa8g+XnfDG1CscYQ1p6IKgFsFFiieA EqXVJGaHZMiLl1YBZK/VJKdlpEE9r/f281kZdPR9NWRqQdY++XSBm8iomp0WkuVYxwEx s4F1X8RzKcIkSstwH7TAa6R1S3/gZv2eNuIrh/aEiNTNYa4aNESVp4VgkecbAV4IJYDl 0t/uc7kswHtkfP/Hj5q+udc9JjyN/Zj7Ahrcl4Nz33jaL/7LiTq0ywYxeRp/USC3S3y/ obYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Nsv7MXVJh2dkGGF11w8uAFVC23CCxgk5LEXEzrK4iec=; b=SFku+Jq5dNazziLMjETd4sAHeO8cHjrD03VI2CoqpoV68Nr1QpF1ME9xtj2EeUAiIb HtBc5vf2tLxEOq7JenS6f81PsVK1AWPu39xrZ40lHzJvOd8iNXVMI2GbW/BhOQ8KKZJY rVDhW3/d9wrtz/jZZgdw6MjAtaoxJwovHjQuBoycGR4jRLvkhGJglitB0S2o453qIUca 0/wwqL8VCpl0+cfv+Auxkb8T91Ux1Q42F6KQ9v1VUy1QENiR6sdVkeLzsWpJa3TbTzow 4DbGGTCjXRJ83d9ljTf9wIQT0MsPdMEezL0SdkoYtNbVGIaveFYqfCuonVc+ghRCyp/J kxfQ== X-Gm-Message-State: ALoCoQmmKlJ6Nka/UfBomUMAxV7fPo9kCkW4e/QLAX7MPxQ7QV4DspVIuUXPm1JxtVniqpvRkhHq X-Received: by 10.28.172.2 with SMTP id v2mr34899929wme.10.1448961366043; Tue, 01 Dec 2015 01:16:06 -0800 (PST) Received: from mms734.qualcomm.mm-sol.com ([37.157.136.206]) by smtp.gmail.com with ESMTPSA id t64sm25290428wmf.23.2015.12.01.01.16.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 01 Dec 2015 01:16:05 -0800 (PST) From: Stanimir Varbanov To: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, dmaengine@vger.kernel.org, Vinod Koul Cc: Rob Herring , Rob Herring , Mark Rutland , Pawel Moll , Ian Campbell , Andy Gross , Archit Taneja , Stanimir Varbanov Subject: [PATCH 3/4] dmaengine: qcom_bam_dma: use correct pipe FIFO size Date: Tue, 1 Dec 2015 11:14:58 +0200 Message-Id: <1448961299-15161-4-git-send-email-stanimir.varbanov@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1448961299-15161-1-git-send-email-stanimir.varbanov@linaro.org> References: <1448961299-15161-1-git-send-email-stanimir.varbanov@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The pipe fifo size register must instruct the bam hw how many hw descriptors can be pushed to fifo. Currently we isntruct the hw with 32KBytes but wrap the tail in bam_start_dma in BAM_P_EVNT_REG on 4095 i.e. 32760. This leads to stalled transactions when the tail wraps. Fix this by use the correct fifo size in BAM_P_FIFO_SIZES register i.e. 32K - 8. Signed-off-by: Stanimir Varbanov --- drivers/dma/qcom_bam_dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/dma/qcom_bam_dma.c b/drivers/dma/qcom_bam_dma.c index 0f06f3b7a72b..6d290de9ab2b 100644 --- a/drivers/dma/qcom_bam_dma.c +++ b/drivers/dma/qcom_bam_dma.c @@ -458,7 +458,7 @@ static void bam_chan_init_hw(struct bam_chan *bchan, */ writel_relaxed(ALIGN(bchan->fifo_phys, sizeof(struct bam_desc_hw)), bam_addr(bdev, bchan->id, BAM_P_DESC_FIFO_ADDR)); - writel_relaxed(BAM_DESC_FIFO_SIZE, + writel_relaxed(BAM_MAX_DATA_SIZE, bam_addr(bdev, bchan->id, BAM_P_FIFO_SIZES)); /* enable the per pipe interrupts, enable EOT, ERR, and INT irqs */