From patchwork Wed Feb 3 18:00:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 61117 Delivered-To: patch@linaro.org Received: by 10.112.43.199 with SMTP id y7csp447702lbl; Wed, 3 Feb 2016 10:01:33 -0800 (PST) X-Received: by 10.98.72.193 with SMTP id q62mr4296737pfi.117.1454522491980; Wed, 03 Feb 2016 10:01:31 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z87si10610812pfa.67.2016.02.03.10.01.31; Wed, 03 Feb 2016 10:01:31 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965039AbcBCSBa (ORCPT + 6 others); Wed, 3 Feb 2016 13:01:30 -0500 Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]:57433 "EHLO cam-admin0.cambridge.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965123AbcBCSB2 (ORCPT ); Wed, 3 Feb 2016 13:01:28 -0500 Received: from edgewater-inn.cambridge.arm.com (edgewater-inn.cambridge.arm.com [10.1.203.121]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id u13I0tWr004488; Wed, 3 Feb 2016 18:00:55 GMT Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 7EFF21AE3924; Wed, 3 Feb 2016 18:00:59 +0000 (GMT) From: Will Deacon To: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Will Deacon , Mark Rutland , Marc Zyngier Subject: [PATCH] dt-bindings: arm, gic-v3: require that reserved cells are always 0 Date: Wed, 3 Feb 2016 18:00:58 +0000 Message-Id: <1454522458-29643-1-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The arm,gic-v3 binding was written with good intentions and doesn't enforce interrupt-cells to be 3, therefore making it easy to extend the irq description in future if necessary: > Cells 4 and beyond are reserved for future use. Unfortunately, this sentence is immediately followed up with: > When the 1st cell has a value of 0 or 1, cells 4 and beyond act as > padding, and may be ignored. It is recommended that padding cells > have a value of 0. Consequently, any extensions to the PPI or SPI interrupt specifiers must be able to work with random crap from legacy DTs, effectively necessitating a new interrupt type in the first cell. Sigh. This patch fixes the text so that additional, reserved cells are required to be zero. This looks like a reasonable thing to require and is already satisifed by the .dts files in-tree. Cc: Mark Rutland Cc: Marc Zyngier Signed-off-by: Will Deacon --- .../devicetree/bindings/interrupt-controller/arm,gic-v3.txt | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Mark Rutland diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt index 7803e77d85cb..007a5b46256a 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt @@ -24,9 +24,8 @@ Main node required properties: 1 = edge triggered 4 = level triggered - Cells 4 and beyond are reserved for future use. When the 1st cell - has a value of 0 or 1, cells 4 and beyond act as padding, and may be - ignored. It is recommended that padding cells have a value of 0. + Cells 4 and beyond are reserved for future use and must have a value + of 0 if present. - reg : Specifies base physical address(s) and size of the GIC registers, in the following order: