From patchwork Mon Apr 25 12:53:54 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 66574 Delivered-To: patch@linaro.org Received: by 10.140.93.198 with SMTP id d64csp1019560qge; Mon, 25 Apr 2016 05:54:19 -0700 (PDT) X-Received: by 10.66.160.201 with SMTP id xm9mr47867529pab.68.1461588859663; Mon, 25 Apr 2016 05:54:19 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 127si6685993pfe.224.2016.04.25.05.54.19; Mon, 25 Apr 2016 05:54:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932283AbcDYMyS (ORCPT + 7 others); Mon, 25 Apr 2016 08:54:18 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:51977 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932139AbcDYMyS (ORCPT ); Mon, 25 Apr 2016 08:54:18 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id u3PCrwGb021104; Mon, 25 Apr 2016 07:53:58 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id u3PCrwDP013482; Mon, 25 Apr 2016 07:53:58 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.224.2; Mon, 25 Apr 2016 07:53:58 -0500 Received: from lta0400828d.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id u3PCrtgR002920; Mon, 25 Apr 2016 07:53:56 -0500 From: Roger Quadros To: CC: , , , , , , Roger Quadros Subject: [PATCH] ARM: dts: dra7xx: Fix compatible string for PCF8575 chip Date: Mon, 25 Apr 2016 15:53:54 +0300 Message-ID: <1461588834-20908-1-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.5.0 MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The boards use a TI variant of the PCF8575 so specify that in the compatible string. Signed-off-by: Roger Quadros --- arch/arm/boot/dts/dra7-evm.dts | 6 +++--- arch/arm/boot/dts/dra72-evm-common.dtsi | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) -- 2.5.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index d272cf1..4fb0ff4 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -556,7 +556,7 @@ }; pcf_lcd: gpio@20 { - compatible = "nxp,pcf8575"; + compatible = "ti,pcf8575", "nxp,pcf8575"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; @@ -567,7 +567,7 @@ }; pcf_gpio_21: gpio@21 { - compatible = "nxp,pcf8575"; + compatible = "ti,pcf8575", "nxp,pcf8575"; reg = <0x21>; lines-initial-states = <0x1408>; gpio-controller; @@ -601,7 +601,7 @@ clock-frequency = <400000>; pcf_hdmi: gpio@26 { - compatible = "nxp,pcf8575"; + compatible = "ti,pcf8575", "nxp,pcf8575"; reg = <0x26>; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi index 2c88050..90a827d 100644 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi @@ -408,7 +408,7 @@ }; pcf_gpio_21: gpio@21 { - compatible = "nxp,pcf8575"; + compatible = "ti,pcf8575", "nxp,pcf8575"; reg = <0x21>; lines-initial-states = <0x1408>; gpio-controller; @@ -440,7 +440,7 @@ clock-frequency = <400000>; pcf_hdmi: pcf8575@26 { - compatible = "nxp,pcf8575"; + compatible = "ti,pcf8575", "nxp,pcf8575"; reg = <0x26>; gpio-controller; #gpio-cells = <2>;