From patchwork Fri Oct 28 08:45:31 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 79863 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp1060847qge; Fri, 28 Oct 2016 01:47:18 -0700 (PDT) X-Received: by 10.99.125.68 with SMTP id m4mr18548281pgn.58.1477644438750; Fri, 28 Oct 2016 01:47:18 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id fc3si10305566pab.267.2016.10.28.01.47.18; Fri, 28 Oct 2016 01:47:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759368AbcJ1IrQ (ORCPT + 7 others); Fri, 28 Oct 2016 04:47:16 -0400 Received: from foss.arm.com ([217.140.101.70]:53870 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S941700AbcJ1Ip4 (ORCPT ); Fri, 28 Oct 2016 04:45:56 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7AEF32B; Fri, 28 Oct 2016 01:45:55 -0700 (PDT) Received: from e107155-lin.cambridge.arm.com (unknown [10.1.210.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 770803F220; Fri, 28 Oct 2016 01:45:54 -0700 (PDT) From: Sudeep Holla To: linux-kernel@vger.kernel.org, Greg Kroah-Hartman Cc: Sudeep Holla , x86@kernel.org, devicetree@vger.kernel.org, Alex Van Brunt Subject: [PATCH 4/4] drivers: base: cacheinfo: support DT overrides for cache properties Date: Fri, 28 Oct 2016 09:45:31 +0100 Message-Id: <1477644331-25559-5-git-send-email-sudeep.holla@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1477644331-25559-1-git-send-email-sudeep.holla@arm.com> References: <1477644331-25559-1-git-send-email-sudeep.holla@arm.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Few architectures like x86, ia64 and s390 derive the cache topology and all the properties using a specific architected mechanism while some other architectures like powerpc all those information id derived from the device tree. On ARM, both the mechanism is used. While all the cache properties can be derived in a architected way, it needs to rely on device tree to get the cache topology information. However there are few platforms where this architected mechanism is broken and the device tree properties can be used to override these incorrect values. This patch adds support for overriding the cache properties values to the values specified in the device tree. Cc: Alex Van Brunt Cc: Greg Kroah-Hartman Signed-off-by: Sudeep Holla --- drivers/base/cacheinfo.c | 121 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 121 insertions(+) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index f19d50bd8925..2376628c599c 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -88,7 +88,120 @@ static inline bool cache_leaves_are_shared(struct cacheinfo *this_leaf, { return sib_leaf->of_node == this_leaf->of_node; } + +/* OF properties to query for a given cache type */ +struct cache_type_info { + const char *size_prop; + const char *line_size_props[2]; + const char *nr_sets_prop; +}; + +static const struct cache_type_info cache_type_info[] = { + { + .size_prop = "cache-size", + .line_size_props = { "cache-line-size", + "cache-block-size", }, + .nr_sets_prop = "cache-sets", + }, { + .size_prop = "i-cache-size", + .line_size_props = { "i-cache-line-size", + "i-cache-block-size", }, + .nr_sets_prop = "i-cache-sets", + }, { + .size_prop = "d-cache-size", + .line_size_props = { "d-cache-line-size", + "d-cache-block-size", }, + .nr_sets_prop = "d-cache-sets", + }, +}; + +static inline int get_cacheinfo_idx(enum cache_type type) +{ + if (type == CACHE_TYPE_UNIFIED) + return 0; + return type; +} + +static void cache_size(struct cacheinfo *this_leaf) +{ + const char *propname; + const __be32 *cache_size; + int ct_idx; + + ct_idx = get_cacheinfo_idx(this_leaf->type); + propname = cache_type_info[ct_idx].size_prop; + + cache_size = of_get_property(this_leaf->of_node, propname, NULL); + if (cache_size) + this_leaf->size = of_read_number(cache_size, 1); +} + +/* not cache_line_size() because that's a macro in include/linux/cache.h */ +static void cache_get_line_size(struct cacheinfo *this_leaf) +{ + const __be32 *line_size; + int i, lim, ct_idx; + + ct_idx = get_cacheinfo_idx(this_leaf->type); + lim = ARRAY_SIZE(cache_type_info[ct_idx].line_size_props); + + for (i = 0; i < lim; i++) { + const char *propname; + + propname = cache_type_info[ct_idx].line_size_props[i]; + line_size = of_get_property(this_leaf->of_node, propname, NULL); + if (line_size) + break; + } + + if (line_size) + this_leaf->coherency_line_size = of_read_number(line_size, 1); +} + +static void cache_nr_sets(struct cacheinfo *this_leaf) +{ + const char *propname; + const __be32 *nr_sets; + int ct_idx; + + ct_idx = get_cacheinfo_idx(this_leaf->type); + propname = cache_type_info[ct_idx].nr_sets_prop; + + nr_sets = of_get_property(this_leaf->of_node, propname, NULL); + if (nr_sets) + this_leaf->number_of_sets = of_read_number(nr_sets, 1); +} + +static void cache_associativity(struct cacheinfo *this_leaf) +{ + unsigned int line_size = this_leaf->coherency_line_size; + unsigned int nr_sets = this_leaf->number_of_sets; + unsigned int size = this_leaf->size; + + /* + * If the cache is fully associative, there is no need to + * check the other properties. + */ + if (!(nr_sets == 1) && (nr_sets > 0 && size > 0 && line_size > 0)) + this_leaf->ways_of_associativity = (size / nr_sets) / line_size; +} + +static void cache_of_override_properties(unsigned int cpu) +{ + int index; + struct cacheinfo *this_leaf; + struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); + + for (index = 0; index < cache_leaves(cpu); index++) { + this_leaf = this_cpu_ci->info_list + index; + cache_size(this_leaf); + cache_get_line_size(this_leaf); + cache_nr_sets(this_leaf); + cache_associativity(this_leaf); + } +} #else +static void cache_of_override_properties(unsigned int cpu) { } static inline int cache_setup_of_node(unsigned int cpu) { return 0; } static inline bool cache_leaves_are_shared(struct cacheinfo *this_leaf, struct cacheinfo *sib_leaf) @@ -171,6 +284,12 @@ static void cache_shared_cpu_map_remove(unsigned int cpu) } } +static void cache_override_properties(unsigned int cpu) +{ + if (of_have_populated_dt()) + return cache_of_override_properties(cpu); +} + static void free_cache_attributes(unsigned int cpu) { if (!per_cpu_cacheinfo(cpu)) @@ -216,6 +335,8 @@ static int detect_cache_attributes(unsigned int cpu) pr_warn("Unable to detect cache hierarchy for CPU %d\n", cpu); goto free_ci; } + + cache_override_properties(cpu); return 0; free_ci: