From patchwork Mon Jan 30 10:02:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 92805 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp1358182qgi; Mon, 30 Jan 2017 02:03:38 -0800 (PST) X-Received: by 10.84.215.149 with SMTP id l21mr30659449pli.16.1485770618254; Mon, 30 Jan 2017 02:03:38 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z30si12143943plh.61.2017.01.30.02.03.38; Mon, 30 Jan 2017 02:03:38 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@baylibre-com.20150623.gappssmtp.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752272AbdA3KDV (ORCPT + 7 others); Mon, 30 Jan 2017 05:03:21 -0500 Received: from mail-wm0-f42.google.com ([74.125.82.42]:35781 "EHLO mail-wm0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752156AbdA3KC1 (ORCPT ); Mon, 30 Jan 2017 05:02:27 -0500 Received: by mail-wm0-f42.google.com with SMTP id b65so25106204wmf.0 for ; Mon, 30 Jan 2017 02:02:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UuFqiL7UFZBOptYwa564ZJUFui00u+cvOWp5bQVJzCc=; b=a3g5iQdw6qca6x3ji1zxWQnRW7GmgCUQ4slFmC9wj8s7OwSHrGJLNU82IjgwRSocpX UKLygRXEkAa3AqhAHGqNd121v+oDKZdgfSXkv0EEZycYCz60yolMHYwe+p74mhlZP5eP OGgchtTPy7uj6mpNjdh2ndjS3gLd2DsX5Wsy3eRSl/CCMka/r8vc3NlDDlwxhqkna+OF b9i4RB7T/qFpmAPhVMEG2GQWiB0S2aQQsTjDGH65D0DAKW4WEfukNtpNw2eg8oBkJaSH F6U0Mb1QwhLgP/rGfKTF8b+yA+XZrLsMMud8HHPwiPX8X3Xempz0xke1aKxKXRywj/kh KBMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UuFqiL7UFZBOptYwa564ZJUFui00u+cvOWp5bQVJzCc=; b=tezYbxDPHFPbRtc7sWVcyDT+AZmchexD1eggeOdadA2NHkOww108T2EtR7tTPucKxN LD50TBZjhZf2Tsjti3cZxQGUcdbIr0ZIOlwAa/1p6vCE7mygOtYAKLsgj2j1FmIbLln5 vaUEEbidjn3x9c2JP3w6o13O6RnpTRyad50FIzI375kWH35SUhOm4lqHE0FlPixlhdA0 CHzZtZ+HvjDPpm3Ei4qxUwzUHpCcfWWHWNoxY+aIfhWFi4LEE0j4kEHM0reXDRY0K8aI LBwmqLjbi7wZtMWhwujLMfj6cIda5OflnYwMPrpdHK612/RooFEJB3uQKY/wHvsCyABl LXfQ== X-Gm-Message-State: AIkVDXLwKQ+jBwCJCOcsa/4KGnH5Wnw6Iy/t7fuop0orU2CdwvPyD08VVpDdwf7mLZ1aJT2y X-Received: by 10.28.62.144 with SMTP id l138mr12477911wma.50.1485770546091; Mon, 30 Jan 2017 02:02:26 -0800 (PST) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id j18sm21939536wrb.33.2017.01.30.02.02.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 30 Jan 2017 02:02:25 -0800 (PST) From: Bartosz Golaszewski To: Kevin Hilman , Sekhar Nori , Patrick Titiano , Michael Turquette , Tejun Heo , Rob Herring , Mark Rutland , Russell King , David Lechner Cc: linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bartosz Golaszewski Subject: [PATCH v7 10/14] sata: ahci-da850: add a workaround for controller instability Date: Mon, 30 Jan 2017 11:02:07 +0100 Message-Id: <1485770531-6772-11-git-send-email-bgolaszewski@baylibre.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1485770531-6772-1-git-send-email-bgolaszewski@baylibre.com> References: <1485770531-6772-1-git-send-email-bgolaszewski@baylibre.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org We have a use case with the da850 SATA controller where at PLL0 frequency of 456MHz (needed to properly service the LCD controller) the chip becomes unstable and the hardreset operation is ignored the first time 50% of times. The sata core driver already retries to resume the link because some controllers ignore writes to the SControl register, but just retrying the resume operation doesn't work - we need to issue he phy/wake reset again to make it work. Reimplement ahci_hardreset() in the driver and poke the controller a couple times before really giving up. Signed-off-by: Bartosz Golaszewski Acked-by: Tejun Heo --- drivers/ata/ahci_da850.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) -- 2.9.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/ata/ahci_da850.c b/drivers/ata/ahci_da850.c index 84c7805..d65088a 100644 --- a/drivers/ata/ahci_da850.c +++ b/drivers/ata/ahci_da850.c @@ -16,7 +16,8 @@ #include #include "ahci.h" -#define DRV_NAME "ahci_da850" +#define DRV_NAME "ahci_da850" +#define HARDRESET_RETRIES 5 /* SATA PHY Control Register offset from AHCI base */ #define SATA_P0PHYCR_REG 0x178 @@ -76,6 +77,29 @@ static int ahci_da850_softreset(struct ata_link *link, return ret; } +static int ahci_da850_hardreset(struct ata_link *link, + unsigned int *class, unsigned long deadline) +{ + int ret, retry = HARDRESET_RETRIES; + bool online; + + /* + * In order to correctly service the LCD controller of the da850 SoC, + * we increased the PLL0 frequency to 456MHz from the default 300MHz. + * + * This made the SATA controller unstable and the hardreset operation + * does not always succeed the first time. Before really giving up to + * bring up the link, retry the reset a couple times. + */ + do { + ret = ahci_do_hardreset(link, class, deadline, &online); + if (online) + return ret; + } while (retry--); + + return ret; +} + static struct ata_port_operations ahci_da850_port_ops = { .inherits = &ahci_platform_ops, .softreset = ahci_da850_softreset, @@ -83,6 +107,8 @@ static struct ata_port_operations ahci_da850_port_ops = { * No need to override .pmp_softreset - it's only used for actual * PMP-enabled ports. */ + .hardreset = ahci_da850_hardreset, + .pmp_hardreset = ahci_da850_hardreset, }; static const struct ata_port_info ahci_da850_port_info = {