From patchwork Mon Jan 30 10:02:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 92801 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp1357969qgi; Mon, 30 Jan 2017 02:03:05 -0800 (PST) X-Received: by 10.84.229.13 with SMTP id b13mr30702331plk.175.1485770585862; Mon, 30 Jan 2017 02:03:05 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 89si12103617plc.324.2017.01.30.02.03.05; Mon, 30 Jan 2017 02:03:05 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@baylibre-com.20150623.gappssmtp.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752493AbdA3KDC (ORCPT + 7 others); Mon, 30 Jan 2017 05:03:02 -0500 Received: from mail-wj0-f181.google.com ([209.85.210.181]:33305 "EHLO mail-wj0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751750AbdA3KCd (ORCPT ); Mon, 30 Jan 2017 05:02:33 -0500 Received: by mail-wj0-f181.google.com with SMTP id un2so3735134wjb.0 for ; Mon, 30 Jan 2017 02:02:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6lDvDDznS2Nk/kgCz+B7lKGksqha8DTLTepcz0wgWw4=; b=qC/Y14YSa6x18AKI0ugzJAytxC5QbrypR83HszGs5irocoRqOyeharvhDczTrWk9Ro WSzlCkmoh4wQ/ghUcqnlAT2ibi9u9Dv3cihZ2szV6nWMDdru36DRpk1AXG3XDW3Fvw/7 BXqtFRILYbNdtcPNgN5y5YY9y97RwaM3CtYSvgESOz0UarCuEp9aUeCEOARgWBAJnmLs YsSucgzKnffRjJsKTkZLd9aPaGL2xte5M9aKO8pnRr4Tig1+ERypzwmEdrePuQRGVejF t1UQtvfOXnuh0J8ePdIIBfpu59CUSTgDN9nVIpzsl0cOQxWJ0eK+7flCN9DtqjGqMscQ Nx2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6lDvDDznS2Nk/kgCz+B7lKGksqha8DTLTepcz0wgWw4=; b=jQwxUwvMf6y5pJda5jDj8wIH5Hc+lfRjFeVDeLXlrXC/u325jO5GWQSUArwolueM/Q 8SE8s3Ns94haN5qEviMa9nG9d0YbKyCHQHKmHq+1ePX9K51Zr0bXf3VCxsbhzNBBQy73 1kRvySr0L/zacuGOqJMJW0TYLjZ+bNxra8PE4LMISGmrHMRrE3Eg6nRMffq23h/AOhg/ aTAHvBJKv9G15wTjYuQ8eUQJMR5uw163Ii6I5G0Ba1HVKSvC3ud9iBk+dCrIRcuh6dWC cHISi/ObSXRvZQJRH6T5gZmZARq3zx1IfBC6LMsKe2fl3Ywk/3aizHMcApadCMHWk4RM L5VQ== X-Gm-Message-State: AIkVDXI17p2970R+2xlqFLia2LUvUm+Ncj/j+6Ce3+s8nsiE6gmq1rvkh07fvBXtkRkH+wN+ X-Received: by 10.223.171.149 with SMTP id s21mr17477593wrc.64.1485770547278; Mon, 30 Jan 2017 02:02:27 -0800 (PST) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id j18sm21939536wrb.33.2017.01.30.02.02.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 30 Jan 2017 02:02:26 -0800 (PST) From: Bartosz Golaszewski To: Kevin Hilman , Sekhar Nori , Patrick Titiano , Michael Turquette , Tejun Heo , Rob Herring , Mark Rutland , Russell King , David Lechner Cc: linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bartosz Golaszewski Subject: [PATCH v7 11/14] sata: ahci-da850: un-hardcode the MPY bits Date: Mon, 30 Jan 2017 11:02:08 +0100 Message-Id: <1485770531-6772-12-git-send-email-bgolaszewski@baylibre.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1485770531-6772-1-git-send-email-bgolaszewski@baylibre.com> References: <1485770531-6772-1-git-send-email-bgolaszewski@baylibre.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org All platforms using this driver now register the SATA refclk. Remove the hardcoded default value from the driver and instead read the rate of the external clock and calculate the required MPY value from it. Signed-off-by: Bartosz Golaszewski Acked-by: Tejun Heo --- drivers/ata/ahci_da850.c | 91 ++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 76 insertions(+), 15 deletions(-) -- 2.9.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/ata/ahci_da850.c b/drivers/ata/ahci_da850.c index d65088a..44bb795 100644 --- a/drivers/ata/ahci_da850.c +++ b/drivers/ata/ahci_da850.c @@ -29,17 +29,8 @@ #define SATA_PHY_TXSWING(x) ((x) << 19) #define SATA_PHY_ENPLL(x) ((x) << 31) -/* - * The multiplier needed for 1.5GHz PLL output. - * - * NOTE: This is currently hardcoded to be suitable for 100MHz crystal - * frequency (which is used by DA850 EVM board) and may need to be changed - * if you would like to use this driver on some other board. - */ -#define DA850_SATA_CLK_MULTIPLIER 7 - static void da850_sata_init(struct device *dev, void __iomem *pwrdn_reg, - void __iomem *ahci_base) + void __iomem *ahci_base, u32 mpy) { unsigned int val; @@ -48,13 +39,61 @@ static void da850_sata_init(struct device *dev, void __iomem *pwrdn_reg, val &= ~BIT(0); writel(val, pwrdn_reg); - val = SATA_PHY_MPY(DA850_SATA_CLK_MULTIPLIER + 1) | SATA_PHY_LOS(1) | - SATA_PHY_RXCDR(4) | SATA_PHY_RXEQ(1) | SATA_PHY_TXSWING(3) | - SATA_PHY_ENPLL(1); + val = SATA_PHY_MPY(mpy) | SATA_PHY_LOS(1) | SATA_PHY_RXCDR(4) | + SATA_PHY_RXEQ(1) | SATA_PHY_TXSWING(3) | SATA_PHY_ENPLL(1); writel(val, ahci_base + SATA_P0PHYCR_REG); } +static u32 ahci_da850_calculate_mpy(unsigned long refclk_rate) +{ + u32 pll_output = 1500000000, needed; + + /* + * We need to determine the value of the multiplier (MPY) bits. + * In order to include the 12.5 multiplier we need to first divide + * the refclk rate by ten. + * + * __div64_32() turned out to be unreliable, sometimes returning + * false results. + */ + WARN((refclk_rate % 10) != 0, "refclk must be divisible by 10"); + needed = pll_output / (refclk_rate / 10); + + /* + * What we have now is (multiplier * 10). + * + * Let's determine the actual register value we need to write. + */ + + switch (needed) { + case 50: + return 0x1; + case 60: + return 0x2; + case 80: + return 0x4; + case 100: + return 0x5; + case 120: + return 0x6; + case 125: + return 0x7; + case 150: + return 0x8; + case 200: + return 0x9; + case 250: + return 0xa; + default: + /* + * We should have divided evenly - if not, return an invalid + * value. + */ + return 0; + } +} + static int ahci_da850_softreset(struct ata_link *link, unsigned int *class, unsigned long deadline) { @@ -126,9 +165,10 @@ static int ahci_da850_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct ahci_host_priv *hpriv; - struct resource *res; void __iomem *pwrdn_reg; + struct resource *res; struct clk *clk; + u32 mpy; int rc; hpriv = ahci_platform_get_resources(pdev); @@ -150,6 +190,27 @@ static int ahci_da850_probe(struct platform_device *pdev) hpriv->clks[0] = clk; } + /* + * The second clock used by ahci-da850 is the external REFCLK. If we + * didn't get it from ahci_platform_get_resources(), let's try to + * specify the con_id in clk_get(). + */ + if (!hpriv->clks[1]) { + clk = clk_get(dev, "refclk"); + if (IS_ERR(clk)) { + dev_err(dev, "unable to obtain the reference clock"); + return -ENODEV; + } else { + hpriv->clks[1] = clk; + } + } + + mpy = ahci_da850_calculate_mpy(clk_get_rate(hpriv->clks[1])); + if (mpy == 0) { + dev_err(dev, "invalid REFCLK multiplier value: 0x%x", mpy); + return -EINVAL; + } + rc = ahci_platform_enable_resources(hpriv); if (rc) return rc; @@ -162,7 +223,7 @@ static int ahci_da850_probe(struct platform_device *pdev) if (!pwrdn_reg) goto disable_resources; - da850_sata_init(dev, pwrdn_reg, hpriv->mmio); + da850_sata_init(dev, pwrdn_reg, hpriv->mmio, mpy); rc = ahci_platform_init_host(pdev, hpriv, &ahci_da850_port_info, &ahci_platform_sht);