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[209.132.180.67]) by mx.google.com with ESMTP id t9si957784pfh.101.2018.03.09.06.49.39; Fri, 09 Mar 2018 06:49:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=hngZcV9T; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751146AbeCIOti (ORCPT + 6 others); Fri, 9 Mar 2018 09:49:38 -0500 Received: from mail-pf0-f193.google.com ([209.85.192.193]:33505 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751102AbeCIOte (ORCPT ); Fri, 9 Mar 2018 09:49:34 -0500 Received: by mail-pf0-f193.google.com with SMTP id q13so1366947pff.0 for ; Fri, 09 Mar 2018 06:49:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xtDznGiITxqvxKs72SRFnvRZXD17YyrDvzNOABYKHS4=; b=hngZcV9TJ46HGP4oe48KtznhoeOGU8B5bE0+Mk7xWT6+cq681/+W/e9kKWsSHT2605 8shLQByMA3XjUjI9BLqJJ6iOQ09LL9ln8+yfwlJOZcW342fYta/CmRhghwYuLDCdt7dC o4k9VSjQqn78Unwxr1AA/8v9StOsst6EN3a7I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xtDznGiITxqvxKs72SRFnvRZXD17YyrDvzNOABYKHS4=; b=C7bLLRipObKxS0j+23CNePeHjKf0ajJFcUpvU9uNlnc6e+mToR6VFTBBolxwhfYkTx IltuykfBwVw5N8KhSxIrdI11tkqIEjO0BOPtWdZ7fDvM8KRI2cW7dCKt1xYlctDKa2VK qfPLYdHMVZs1nl8sRfchYdR1sNhpP+VJhDaHed0L7XJR4WwojEhJruMVEKtbIXDzbuOI cEEaw2NA0COGDmSHumjfqkKFdJ69xArm1n4GSfbE0mkIDQFrC4KgDET5s461QQ0A+L0s FgjD0j9GsqXu9XAIz9kjyiI5cMUa24w1WfFaD+XBb3ldT35Y7cOc0X/fs49yw2OtL/sq 4Hkg== X-Gm-Message-State: APf1xPCq1Jgh+331hI43KXRCuvHGm2tOl5iXpK86IrU7oDh2Ct3xUzPQ aMYngTZueXwLKFnKyUDLmKfqYw== X-Received: by 10.98.70.198 with SMTP id o67mr30056394pfi.173.1520606974196; Fri, 09 Mar 2018 06:49:34 -0800 (PST) Received: from localhost.localdomain ([104.237.91.63]) by smtp.gmail.com with ESMTPSA id o184sm2919071pga.16.2018.03.09.06.49.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Mar 2018 06:49:32 -0800 (PST) From: Shawn Guo To: Kishon Vijay Abraham I Cc: Rob Herring , Jianguo Sun , Jiancheng Xue , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pengcheng Li , Shawn Guo Subject: [PATCH v5 1/2] dt-bindings: add bindings doc for HiSilicon INNO USB2 PHY Date: Fri, 9 Mar 2018 22:47:00 +0800 Message-Id: <1520606821-22582-2-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1520606821-22582-1-git-send-email-shawn.guo@linaro.org> References: <1520606821-22582-1-git-send-email-shawn.guo@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Pengcheng Li It adds device tree bindings document for HiSilicon INNO USB2 PHY. Signed-off-by: Pengcheng Li Signed-off-by: Jiancheng Xue Signed-off-by: Shawn Guo Reviewed-by: Rob Herring --- .../devicetree/bindings/phy/phy-hisi-inno-usb2.txt | 71 ++++++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt new file mode 100644 index 000000000000..0d70c8341095 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt @@ -0,0 +1,71 @@ +Device tree bindings for HiSilicon INNO USB2 PHY + +Required properties: +- compatible: Should be one of the following strings: + "hisilicon,inno-usb2-phy", + "hisilicon,hi3798cv200-usb2-phy". +- reg: Should be the address space for PHY configuration register in peripheral + controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798CV200 SoC. +- clocks: The phandle and clock specifier pair for INNO USB2 PHY device + reference clock. +- resets: The phandle and reset specifier pair for INNO USB2 PHY device reset + signal. +- #address-cells: Must be 1. +- #size-cells: Must be 0. + +The INNO USB2 PHY device should be a child node of peripheral controller that +contains the PHY configuration register, and each device suppports up to 2 PHY +ports which are represented as child nodes of INNO USB2 PHY device. + +Required properties for PHY port node: +- reg: The PHY port instance number. +- #phy-cells: Defined by generic PHY bindings. Must be 0. +- resets: The phandle and reset specifier pair for PHY port reset signal. + +Refer to phy/phy-bindings.txt for the generic PHY binding properties + +Example: + +perictrl: peripheral-controller@8a20000 { + compatible = "hisilicon,hi3798cv200-perictrl", "simple-mfd"; + reg = <0x8a20000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8a20000 0x1000>; + + usb2_phy1: usb2-phy@120 { + compatible = "hisilicon,hi3798cv200-usb2-phy"; + reg = <0x120 0x4>; + clocks = <&crg HISTB_USB2_PHY1_REF_CLK>; + resets = <&crg 0xbc 4>; + #address-cells = <1>; + #size-cells = <0>; + + usb2_phy1_port0: phy@0 { + reg = <0>; + #phy-cells = <0>; + resets = <&crg 0xbc 8>; + }; + + usb2_phy1_port1: phy@1 { + reg = <1>; + #phy-cells = <0>; + resets = <&crg 0xbc 9>; + }; + }; + + usb2_phy2: usb2-phy@124 { + compatible = "hisilicon,hi3798cv200-usb2-phy"; + reg = <0x124 0x4>; + clocks = <&crg HISTB_USB2_PHY2_REF_CLK>; + resets = <&crg 0xbc 6>; + #address-cells = <1>; + #size-cells = <0>; + + usb2_phy2_port0: phy@0 { + reg = <0>; + #phy-cells = <0>; + resets = <&crg 0xbc 10>; + }; + }; +};