From patchwork Wed Jul 8 08:56:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 235045 Delivered-To: patch@linaro.org Received: by 2002:a92:d244:0:0:0:0:0 with SMTP id v4csp242240ilg; Wed, 8 Jul 2020 01:56:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzMmy7F/awnuNV82icVXXmQ/mri/y4g7LPOeuKxpQIhEv+sPHHYEUku1vPo6MWtoGZbTmB4 X-Received: by 2002:aa7:d049:: with SMTP id n9mr60341498edo.39.1594198585171; Wed, 08 Jul 2020 01:56:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1594198585; cv=none; d=google.com; s=arc-20160816; b=avqXBAxxrblLcRt+Kohv2LxfjPoR29Ccprc0WHC0BGJCLRIaU7YgArHrfRoPIOrVUU h8vezsClj4NhsENHgqX/rWDAvUJFhYsZnJJFuo21qZ8zUNIBIOwFzXfxb586f8r9HvUO V7zMRij9CvpyOmfJp9PS9vXY77sEysTW+lO9OvQWP3JYsR7RtCw6nnOMpD8pgJEm57aN uxRbh9TTUAMQkq43qMhR18UzJQkirRjb9EKU3baGKAA3ajXtG/W2QNU01S+KSmCkDz92 GjNXWXDBYizenQJNGnpvnlHwFavRz2r4o/fUyPp8kEJfCE5mudhqokH7rnhRgRckn2Tf unlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=2U1VW8k4uCUqiEKbrTx03lZXSLK/OyDwhLjQlGvpJXk=; b=hTtoqcFw1roqrB5agBY6Bz/cm5qsp3zq6unOo0BH2qubbQ4Is8WbRVYOUweFWrBn9I lHfyQ4x1FgTFhJQgyRbJfd9+Sgmxbg5yc6SsJ5jFje2KCGWcUNxYyt4/UcDXI0lO3z7R 9fF7UUNILYD3MoAheL8X/4jhrI7EM2a97Xl29utOkJSbjJeJFyrw5F97srUDCzoNsEKs PBKDrW6k6H6x05OC4RgQT4ZjByYdz7ublkQnUKhPv/au7jhAOrsfpxNksRY0VcT2L2nQ P6VcoRJi/f9qWibCMHjRsVfcSA6J0SmC+zPojmA7bI1MPVjXFETUM5T3Hidt95R80WQ0 itLw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id v19si15207906ejj.608.2020.07.08.01.56.25; Wed, 08 Jul 2020 01:56:25 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727903AbgGHI4Y (ORCPT + 6 others); Wed, 8 Jul 2020 04:56:24 -0400 Received: from mx.socionext.com ([202.248.49.38]:18942 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726144AbgGHI4Y (ORCPT ); Wed, 8 Jul 2020 04:56:24 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 08 Jul 2020 17:56:22 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id CC8A360060; Wed, 8 Jul 2020 17:56:22 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Wed, 8 Jul 2020 17:56:22 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 99C111A0507; Wed, 8 Jul 2020 17:56:22 +0900 (JST) From: Kunihiko Hayashi To: Rob Herring , Masahiro Yamada Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Kunihiko Hayashi Subject: [PATCH] arm64: dts: uniphier: Add missing clock-names and reset-names to pcie-phy Date: Wed, 8 Jul 2020 17:56:18 +0900 Message-Id: <1594198578-29238-1-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds missing clock-names and reset-names to pcie-phy node according to Documentation/devicetree/bindings/phy/socionext,uniphier-pcie.yaml. Signed-off-by: Kunihiko Hayashi --- arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 ++ arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 2 ++ 2 files changed, 4 insertions(+) -- 2.7.4 diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index f4a56b2..a87b8a6 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -936,7 +936,9 @@ compatible = "socionext,uniphier-ld20-pcie-phy"; reg = <0x66038000 0x4000>; #phy-cells = <0>; + clock-names = "link"; clocks = <&sys_clk 24>; + reset-names = "link"; resets = <&sys_rst 24>; socionext,syscon = <&soc_glue>; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi index 72f1688..0e52dadf 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi @@ -833,7 +833,9 @@ compatible = "socionext,uniphier-pxs3-pcie-phy"; reg = <0x66038000 0x4000>; #phy-cells = <0>; + clock-names = "link"; clocks = <&sys_clk 24>; + reset-names = "link"; resets = <&sys_rst 24>; socionext,syscon = <&soc_glue>; };