From patchwork Mon Jul 19 02:31:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 479803 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp3716599jao; Sun, 18 Jul 2021 19:31:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxZVTGzsc/hbsJDbZeKXaPjM0YyoJ9jWnA8LPNTZEqy7/sxs54apDgNAenaURSh+ds6hTdn X-Received: by 2002:a05:6638:14c1:: with SMTP id l1mr14257637jak.97.1626661879545; Sun, 18 Jul 2021 19:31:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626661879; cv=none; d=google.com; s=arc-20160816; b=q3x7diclCBVRYEaX8xf5YHLbSzpKOt8QYMsI4n1jyBH2gOdVphdhVe7K8Denmq0x2L 2nNgj9gSAZBi1LcSo1ph3agkYCeV1L9a3OhSXdtFlxklkoQETiD+KuLHgLh3svzJ0agq ZNst5FFqLxHwMwXxiNJK/XiwAXNQunCcY8srWYnY1nLtIBv6vtiMLy6HTKVwWQ0CdcXf HeAvOW86Fb8NSqVuFxVD0g3nmtTXaYgQLPDYEyOtM/lJUHjZu2xpaGQx6QUoSPPKQuBx bOo2VfZI8vOEZfKanPM8weQg7yihrPLL5wcZX5+F6PB7B8VGTeArLBBEA38F0Suyg4o7 p42w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from; bh=/zUsl1Kbisa4+KB1QrdbTtxGzT3H/GbgWXYeWnLgqoA=; b=nuFiZHZlV7ak7c5mTREVBUohWcpS4DK0D0/t6dqHLZed/a5J3nfE3YaPVJHWJFcfVR zwluo4mBI7p9pwIH1ZiBTIDmgvn6K+BuNYmakNK4DYC4VlYH59IsiG43/8irfoS4u32l VB/IICSH0HMs1xs38KbJuBP9TdjeUHYKNcfqH9dFVaIIWjM74RaeDndUB5nk/59LiuG6 LGqCFMWhqQt3Cg8GQ/w2CjlO9UY0VhnQ8W0t62zQi6IQYjM3/zBFoWTSgrg/5uKwl0A4 /KjLr+YhAm1j7P3FPtC5hNcAkOsKooOuOnWFF3mgbA2ABAcGKNPaKO7Bh/0efbKov6Ht mpbA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id k12si18970921ilc.36.2021.07.18.19.31.19; Sun, 18 Jul 2021 19:31:19 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234260AbhGSCeP (ORCPT + 7 others); Sun, 18 Jul 2021 22:34:15 -0400 Received: from mx.socionext.com ([202.248.49.38]:22293 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233713AbhGSCeO (ORCPT ); Sun, 18 Jul 2021 22:34:14 -0400 Received: from unknown (HELO kinkan2-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 19 Jul 2021 11:31:14 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan2-ex.css.socionext.com (Postfix) with ESMTP id ACA95205902A; Mon, 19 Jul 2021 11:31:14 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Mon, 19 Jul 2021 11:31:14 +0900 Received: from plum.e01.socionext.com (unknown [10.212.243.119]) by kinkan2.css.socionext.com (Postfix) with ESMTP id 6B030B633F; Mon, 19 Jul 2021 11:31:14 +0900 (JST) From: Kunihiko Hayashi To: Srinivas Kandagatla , Rob Herring Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Kunihiko Hayashi Subject: [PATCH v2 1/2] dt-bindings: nvmem: Extend patternProperties to optionally indicate bit position Date: Mon, 19 Jul 2021 11:31:03 +0900 Message-Id: <1626661864-15473-2-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1626661864-15473-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1626661864-15473-1-git-send-email-hayashi.kunihiko@socionext.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Allow to extend expression of sub nodes to optionally indicate bit position. This extension is needed to distinguish between different bit positions in the same address. For example, there are two nvmem nodes starting with bit 4 and bit 0 at the same address 0x54. In this case, it can be expressed as follows. trim@54,4 { reg = <0x54 1>; bits = <4 2>; }; trim@54,0 { reg = <0x54 1>; bits = <0 4>; }; Signed-off-by: Kunihiko Hayashi --- Documentation/devicetree/bindings/nvmem/nvmem.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/nvmem/nvmem.yaml b/Documentation/devicetree/bindings/nvmem/nvmem.yaml index b8dc3d2..9dfe196 100644 --- a/Documentation/devicetree/bindings/nvmem/nvmem.yaml +++ b/Documentation/devicetree/bindings/nvmem/nvmem.yaml @@ -40,7 +40,7 @@ properties: maxItems: 1 patternProperties: - "^.*@[0-9a-f]+$": + "^.*@[0-9a-f]+(,[0-9]+)?$": type: object properties: