From patchwork Thu Jan 19 14:26:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Polimera X-Patchwork-Id: 644351 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E091EC6379F for ; Thu, 19 Jan 2023 14:27:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231338AbjASO1G (ORCPT ); Thu, 19 Jan 2023 09:27:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231372AbjASO1D (ORCPT ); Thu, 19 Jan 2023 09:27:03 -0500 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A12ED6F317; Thu, 19 Jan 2023 06:27:02 -0800 (PST) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 30J4cTZw032334; Thu, 19 Jan 2023 14:27:00 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=eo2nQg77us1PQ8ET6X6MkgsO2Gdmg3yPFXTsx/qwwBQ=; b=RnNFNETsfFGMOkDMYEOdzp1WBFDn/iQKDswrwQy1ic/8rlD5aJuYHY2CHam7a+9t2oi9 eoXIefhDCWVARoR9isjDzYEqjSffODIi9YKBJiCqpT7mFnFuA3Uch7hlF8Mbug65+A+U fhUoG5BOjlVxnRKm18tJRPfnmVU2k55cPTmcGwJ3XFRBG0TZXaZ4xwZQnKiK760VsU4K 9y1vyIdOcFMMIaLqA1Yh0VaaYj5IhFjPSrUVrTM7vJ9mFM1O9Orqcnrk8AshicrJUyC7 KSjmVPihB4z/rvKCmPpucy1JgBj6NQqaHfriC68/VqFKbsRjN8aPvSyCaw+n8+Pwn6PE 3A== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3n6r59a304-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 19 Jan 2023 14:27:00 +0000 Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 30JEQxUY001894 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 19 Jan 2023 14:26:59 GMT Received: from vpolimer-linux.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Thu, 19 Jan 2023 06:26:54 -0800 From: Vinod Polimera To: , , , CC: Vinod Polimera , , , , , , , , , , , Subject: [PATCH Resend v11 02/15] drm/msm/dp: use atomic callbacks for DP bridge ops Date: Thu, 19 Jan 2023 19:56:20 +0530 Message-ID: <1674138393-475-3-git-send-email-quic_vpolimer@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1674138393-475-1-git-send-email-quic_vpolimer@quicinc.com> References: <1674138393-475-1-git-send-email-quic_vpolimer@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: v5gDLqtZPtNJ1GP0-Z-FJLrvY6KhMdfz X-Proofpoint-GUID: v5gDLqtZPtNJ1GP0-Z-FJLrvY6KhMdfz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-01-19_09,2023-01-19_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 mlxscore=0 mlxlogscore=959 malwarescore=0 priorityscore=1501 bulkscore=0 suspectscore=0 phishscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301190115 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Use atomic variants for DP bridge callback functions so that the atomic state can be accessed in the interface drivers. The atomic state will help the driver find out if the display is in self refresh state. Signed-off-by: Sankeerth Billakanti Signed-off-by: Vinod Polimera Reviewed-by: Dmitry Baryshkov Reviewed-by: Douglas Anderson --- drivers/gpu/drm/msm/dp/dp_display.c | 9 ++++++--- drivers/gpu/drm/msm/dp/dp_drm.c | 6 +++--- drivers/gpu/drm/msm/dp/dp_drm.h | 9 ++++++--- 3 files changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index bde1a7c..985287e 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -1652,7 +1652,8 @@ int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, return 0; } -void dp_bridge_enable(struct drm_bridge *drm_bridge) +void dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, + struct drm_bridge_state *old_bridge_state) { struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge); struct msm_dp *dp = dp_bridge->dp_display; @@ -1707,7 +1708,8 @@ void dp_bridge_enable(struct drm_bridge *drm_bridge) mutex_unlock(&dp_display->event_mutex); } -void dp_bridge_disable(struct drm_bridge *drm_bridge) +void dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, + struct drm_bridge_state *old_bridge_state) { struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge); struct msm_dp *dp = dp_bridge->dp_display; @@ -1718,7 +1720,8 @@ void dp_bridge_disable(struct drm_bridge *drm_bridge) dp_ctrl_push_idle(dp_display->ctrl); } -void dp_bridge_post_disable(struct drm_bridge *drm_bridge) +void dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, + struct drm_bridge_state *old_bridge_state) { struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge); struct msm_dp *dp = dp_bridge->dp_display; diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c index 275370f..3252d50 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_drm.c @@ -94,9 +94,9 @@ static const struct drm_bridge_funcs dp_bridge_ops = { .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, .atomic_reset = drm_atomic_helper_bridge_reset, - .enable = dp_bridge_enable, - .disable = dp_bridge_disable, - .post_disable = dp_bridge_post_disable, + .atomic_enable = dp_bridge_atomic_enable, + .atomic_disable = dp_bridge_atomic_disable, + .atomic_post_disable = dp_bridge_atomic_post_disable, .mode_set = dp_bridge_mode_set, .mode_valid = dp_bridge_mode_valid, .get_modes = dp_bridge_get_modes, diff --git a/drivers/gpu/drm/msm/dp/dp_drm.h b/drivers/gpu/drm/msm/dp/dp_drm.h index 250f7c6..afe79b8 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.h +++ b/drivers/gpu/drm/msm/dp/dp_drm.h @@ -23,9 +23,12 @@ struct drm_connector *dp_drm_connector_init(struct msm_dp *dp_display, struct dr struct drm_bridge *dp_bridge_init(struct msm_dp *dp_display, struct drm_device *dev, struct drm_encoder *encoder); -void dp_bridge_enable(struct drm_bridge *drm_bridge); -void dp_bridge_disable(struct drm_bridge *drm_bridge); -void dp_bridge_post_disable(struct drm_bridge *drm_bridge); +void dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, + struct drm_bridge_state *old_bridge_state); +void dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, + struct drm_bridge_state *old_bridge_state); +void dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, + struct drm_bridge_state *old_bridge_state); enum drm_mode_status dp_bridge_mode_valid(struct drm_bridge *bridge, const struct drm_display_info *info, const struct drm_display_mode *mode);