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[209.132.180.67]) by mx.google.com with ESMTP id lq2si18862372pab.168.2014.05.19.03.00.01; Mon, 19 May 2014 03:00:01 -0700 (PDT) Received-SPF: none (google.com: devicetree-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753302AbaESKAA (ORCPT + 8 others); Mon, 19 May 2014 06:00:00 -0400 Received: from fw-tnat.austin.arm.com ([217.140.110.23]:14236 "EHLO collaborate-mta1.arm.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750993AbaESKAA (ORCPT ); Mon, 19 May 2014 06:00:00 -0400 Received: from arm.com (e102109-lin.cambridge.arm.com [10.1.203.182]) by collaborate-mta1.arm.com (Postfix) with ESMTPS id A128B13FA3B; Mon, 19 May 2014 04:59:51 -0500 (CDT) Date: Mon, 19 May 2014 10:59:49 +0100 From: Catalin Marinas To: Thomas Petazzoni Cc: Russell King , Will Deacon , "devicetree@vger.kernel.org" , Grant Likely , Rob Herring , Arnd Bergmann , Albin Tonnerre , "linux-arm-kernel@lists.infradead.org" , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , Tawfik Bayouk , Nadav Haklai , Lior Amsalem , Ezequiel Garcia Subject: Re: [PATCHv5 4/4] ARM: mvebu: use pci_ioremap_set_mem_type() to map PCI I/O as strongly ordered Message-ID: <20140519095949.GD5113@arm.com> References: <1400487234-4501-1-git-send-email-thomas.petazzoni@free-electrons.com> <1400487234-4501-5-git-send-email-thomas.petazzoni@free-electrons.com> MIME-Version: 1.0 In-Reply-To: <1400487234-4501-5-git-send-email-thomas.petazzoni@free-electrons.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: catalin.marinas@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.216.178 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Content-Disposition: inline On Mon, May 19, 2014 at 09:13:54AM +0100, Thomas Petazzoni wrote: > Part of the workaround for the PCIe/SMP/PL310 deadlock on Armada > 375/38x is to map PCI mappings strongly ordered. Mapping PCI memory > regions as strongly ordered was already done thanks to the > arch_ioremap_caller mechanism. This patch does the same for the PCI > I/O regions by using the new pci_ioremap_set_mem_type() function. > > Signed-off-by: Thomas Petazzoni > --- > arch/arm/mach-mvebu/coherency.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c > index f6be9c6..0215614 100644 > --- a/arch/arm/mach-mvebu/coherency.c > +++ b/arch/arm/mach-mvebu/coherency.c > @@ -335,6 +335,7 @@ static void __init armada_375_380_coherency_init(struct device_node *np) > > coherency_cpu_base = of_iomap(np, 0); > arch_ioremap_caller = armada_pcie_wa_ioremap_caller; > + pci_ioremap_set_mem_type(MT_UNCACHED); The patch is fine but for this to work in the UP case we need to fix MT_UNCACHED definition for sections. It seems to create SO memory but not necessarily writable (unless I miss something). Anyway, untested, something like this: diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index b68c6b22e1c8..db1bf8cb3a3e 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -267,7 +267,7 @@ static struct mem_type mem_types[] = { [MT_UNCACHED] = { .prot_pte = PROT_PTE_DEVICE, .prot_l1 = PMD_TYPE_TABLE, - .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, + .prot_sect = PROT_SECT_DEVICE, .domain = DOMAIN_IO, }, [MT_CACHECLEAN] = { @@ -461,6 +461,7 @@ static void __init build_mem_type_table(void) mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN; mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN; mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN; + mem_types[MT_UNCACHED].prot_sect |= PMD_SECT_XN; /* Also setup NX memory mapping */ mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN;