From patchwork Mon Oct 31 14:55:24 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 80207 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp158071qge; Mon, 31 Oct 2016 07:56:00 -0700 (PDT) X-Received: by 10.99.114.73 with SMTP id c9mr41648401pgn.175.1477925760160; Mon, 31 Oct 2016 07:56:00 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n28si15661137pfa.112.2016.10.31.07.55.59; Mon, 31 Oct 2016 07:56:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964977AbcJaOzl (ORCPT + 7 others); Mon, 31 Oct 2016 10:55:41 -0400 Received: from mail-wm0-f45.google.com ([74.125.82.45]:38344 "EHLO mail-wm0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964848AbcJaOzg (ORCPT ); Mon, 31 Oct 2016 10:55:36 -0400 Received: by mail-wm0-f45.google.com with SMTP id n67so233665004wme.1 for ; Mon, 31 Oct 2016 07:55:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OolcrjjlMeRRjT56qD4czoJkw3aDGQOJ4dCgajkU8SI=; b=kCp76m59cFIEq36I+1fizojciZFbNH8EDcyQ65+z2fBNvAl3VsO5+0eS1pFEYh1dyW d3gTr41XCfGBrNaMzRFtSaxL2XkTlbAXcF5aHqzS/n9hWSLvShZ8PxrM0nCDXbmNVXVd UL6HsNTrFz6T+EZAZS0ZBo0OU0LokhnaGriXQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OolcrjjlMeRRjT56qD4czoJkw3aDGQOJ4dCgajkU8SI=; b=PUrkTfk0qJ29h2UpZQlxeJIrxyiUqJxNWF9vDIZ3D0m0lf85dnwug+tZA8jWyr1ZRJ qfTSvnjbniXbzMljtRVXJ6fhJpmsycDdsUpcov9oFh/1bFzRbMrV1ahA44jr5uI3ehZW AybmTIUjPMTm4S9dK6QztsyuTanaZ0gfY0oTZHRsOJD8iaRNlEQw/d9nW7kpY2iT2TLY IpAwnioNsZCdKBG7KO8lDw0hj5vlVYV8rNPvSPL0BspgdKJO8NKzQGQGXrrMz2wwJgUr VrHkt34IZlAxA2OiN11waQeTa1lvluYAPUScr7+ve10ClQE+CXzSNNlbFQ+Xg8Bgzc9f 3WKQ== X-Gm-Message-State: ABUngvfsmRDEwHtmjHbMLTxY8uS5yS92N3wFT6tabCTOIA5CXuYkKdqXf62in/BQJ2dAV1J8 X-Received: by 10.194.122.67 with SMTP id lq3mr28440476wjb.54.1477925729830; Mon, 31 Oct 2016 07:55:29 -0700 (PDT) Received: from mms-0441.wifi.mm-sol.com ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id xq9sm30354970wjb.35.2016.10.31.07.55.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 31 Oct 2016 07:55:29 -0700 (PDT) From: Georgi Djakov To: sboyd@codeaurora.org, mturquette@baylibre.com Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v7 1/3] clk: qcom: Add A53 PLL support Date: Mon, 31 Oct 2016 16:55:24 +0200 Message-Id: <20161031145526.5023-2-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20161031145526.5023-1-georgi.djakov@linaro.org> References: <20161031145526.5023-1-georgi.djakov@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for the PLL, which generates the higher range of CPU frequencies on MSM8916 platforms. Signed-off-by: Georgi Djakov --- .../devicetree/bindings/clock/qcom,a53pll.txt | 20 +++++ drivers/clk/qcom/Kconfig | 9 +++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/a53-pll.c | 94 ++++++++++++++++++++++ 4 files changed, 124 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,a53pll.txt create mode 100644 drivers/clk/qcom/a53-pll.c -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/clock/qcom,a53pll.txt b/Documentation/devicetree/bindings/clock/qcom,a53pll.txt new file mode 100644 index 000000000000..6a8c03bfbcb5 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,a53pll.txt @@ -0,0 +1,20 @@ +MSM8916 A53 PLL Binding +--------------- +The A53 PLL on MSM8916 platforms is the main CPU PLL used for frequencies +above 1GHz. + +Required properties : +- compatible : Shall contain only one of the following: + + "qcom,a53pll-msm8916" + +- reg : shall contain base register location and length +- #clock-cells : must be set to <0> + +Example: + + a53pll: a53pll@b016000 { + compatible = "qcom,a53pll-msm8916"; + reg = <0x0b016000 0x40>; + #clock-cells = <0>; + }; diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 0146d3c2547f..a889f0b14b54 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -150,3 +150,12 @@ config MSM_MMCC_8996 Support for the multimedia clock controller on msm8996 devices. Say Y if you want to support multimedia devices such as display, graphics, video encode/decode, camera, etc. + +config QCOM_A53PLL + bool "A53 PLL" + depends on COMMON_CLK_QCOM + help + Support for the A53 PLL on some Qualcomm devices. It provides + support for CPU frequencies above 1GHz. + Say Y if you want to support CPU frequency scaling on devices + such as MSM8916. diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 1fb1f5476cb0..7d27f47f0c92 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -29,3 +29,4 @@ obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o +obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o diff --git a/drivers/clk/qcom/a53-pll.c b/drivers/clk/qcom/a53-pll.c new file mode 100644 index 000000000000..40610d4076dd --- /dev/null +++ b/drivers/clk/qcom/a53-pll.c @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2016, Linaro Limited + * Copyright (c) 2014, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "clk-pll.h" +#include "clk-regmap.h" + +static const struct pll_freq_tbl a53pll_freq[] = { + { 998400000, 52, 0x0, 0x1, 0 }, + { 1094400000, 57, 0x0, 0x1, 0 }, + { 1152000000, 62, 0x0, 0x1, 0 }, + { 1209600000, 65, 0x0, 0x1, 0 }, + { 1401600000, 73, 0x0, 0x1, 0 }, +}; + +static const struct regmap_config a53pll_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x40, + .fast_io = true, + .val_format_endian = REGMAP_ENDIAN_LITTLE, +}; + +static const struct of_device_id qcom_a53pll_match_table[] = { + { .compatible = "qcom,a53pll-msm8916" }, + { } +}; + +static int qcom_a53pll_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct clk_pll *pll; + struct resource *res; + void __iomem *base; + struct regmap *regmap; + struct clk_init_data init = { }; + + pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); + if (!pll) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap = devm_regmap_init_mmio(dev, base, &a53pll_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + pll->l_reg = 0x04; + pll->m_reg = 0x08; + pll->n_reg = 0x0c; + pll->config_reg = 0x14; + pll->mode_reg = 0x00; + pll->status_reg = 0x1c; + pll->status_bit = 16; + pll->freq_tbl = a53pll_freq; + + init.name = "a53pll"; + init.parent_names = (const char *[]){ "xo" }; + init.num_parents = 1; + init.ops = &clk_pll_sr2_ops; + init.flags = CLK_IS_CRITICAL; + pll->clkr.hw.init = &init; + + return devm_clk_register_regmap(dev, &pll->clkr); +} + +static struct platform_driver qcom_a53pll_driver = { + .probe = qcom_a53pll_probe, + .driver = { + .name = "qcom-a53pll", + .of_match_table = qcom_a53pll_match_table, + }, +}; + +builtin_platform_driver(qcom_a53pll_driver);