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[209.132.180.67]) by mx.google.com with ESMTP id e63si13137589pgc.239.2018.12.18.07.03.29; Tue, 18 Dec 2018 07:03:29 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HxFWH4zm; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726850AbeLRPD2 (ORCPT + 6 others); Tue, 18 Dec 2018 10:03:28 -0500 Received: from mail-pg1-f193.google.com ([209.85.215.193]:33917 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726848AbeLRPD2 (ORCPT ); Tue, 18 Dec 2018 10:03:28 -0500 Received: by mail-pg1-f193.google.com with SMTP id j10so6727103pga.1 for ; Tue, 18 Dec 2018 07:03:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v4xtujsTt51xjeBlCqtpiwVFI+MMIJI2gQm9S+Vb5IU=; b=HxFWH4zm9VyHcUeDTZblNdLNCFIFYBvQP8phho0YEoV5uUBZEwyn5+5UpHrA4BGx3v HIJ7xsbJfRAJCjM3EBpkpVyiAe9jvDGR93r709LHS3Vz94eC8Gcyd7HDu4dpiaUFHlc6 C50+uBYf8TfYjB+jOhBR45/RZmhBtTF17wpqk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v4xtujsTt51xjeBlCqtpiwVFI+MMIJI2gQm9S+Vb5IU=; b=MWdr/K682jrrrYMWz4RxSrN2dvsaTm8d93bMRXUBty7BBZtxPHT0Bw4ObH5qdNtE0K OBkCZPAJMU0KapQ38HNGGSi/mLkgun+OO6EuwwLurMBOkf8CguwN05Q/Ai9PntlNq/By SjlXLMa+c2/1xDOw128lSRIz0VNdA7lb3YzZ3Bn3TldWIpgJeCsXm7/DY/vyHE9trE6O U+m88PuExNLQK3DNP30pqzwWoN3IvzPDGbuG+7YAZgxWevPucS312Gn4ZjKkCY2ob++g AtgruWYoxQSc4YooYAzDrU3gP1ct1K0Vtr0ucDVxh6c7Gcru7LQseF/h/b1UDynhUXMc wK9A== X-Gm-Message-State: AA+aEWY9FUt7bV0oe7FS8m7XlJNbk2ej39+yN0Po1aQ3K4iuMnwIsJxg o/S9JfdJETRIWNd2xaeYIuV3 X-Received: by 2002:a63:7c41:: with SMTP id l1mr15797012pgn.45.1545145407166; Tue, 18 Dec 2018 07:03:27 -0800 (PST) Received: from localhost.localdomain ([2409:4072:702:382e:8c68:d268:ed20:5f25]) by smtp.gmail.com with ESMTPSA id m198sm28798688pga.10.2018.12.18.07.03.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Dec 2018 07:03:26 -0800 (PST) From: Manivannan Sadhasivam To: olof@lixom.net, arnd@arndb.de, arm@kernel.org, linux-arm-kernel@lists.infradead.org Cc: robh+dt@kernel.org, gregkh@linuxfoundation.org, jslaby@suse.com, linux-unisoc@lists.infradead.org, afaerber@suse.de, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-serial@vger.kernel.org, amit.kucheria@linaro.org, linus.walleij@linaro.org, zhao_steven@263.net, Manivannan Sadhasivam Subject: [PATCH v7 04/11] ARM: dts: Add devicetree for RDA8810PL SoC Date: Tue, 18 Dec 2018 20:32:31 +0530 Message-Id: <20181218150238.23010-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181218150238.23010-1-manivannan.sadhasivam@linaro.org> References: <20181218150238.23010-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add initial device tree for RDA8810PL SoC from RDA Microelectronics. Signed-off-by: Andreas Färber Signed-off-by: Manivannan Sadhasivam Acked-by: Arnd Bergmann --- arch/arm/boot/dts/rda8810pl.dtsi | 86 ++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 arch/arm/boot/dts/rda8810pl.dtsi -- 2.17.1 diff --git a/arch/arm/boot/dts/rda8810pl.dtsi b/arch/arm/boot/dts/rda8810pl.dtsi new file mode 100644 index 000000000000..15547b138977 --- /dev/null +++ b/arch/arm/boot/dts/rda8810pl.dtsi @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * RDA8810PL SoC + * + * Copyright (c) 2017 Andreas Färber + * Copyright (c) 2018 Manivannan Sadhasivam + */ + +/ { + compatible = "rda,8810pl"; + interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + reg = <0x0>; + }; + }; + + sram@100000 { + compatible = "mmio-sram"; + reg = <0x100000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + }; + + apb@20800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20800000 0x100000>; + + intc: interrupt-controller@0 { + compatible = "rda,8810pl-intc"; + reg = <0x0 0x1000>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + apb@20900000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20900000 0x100000>; + }; + + apb@20a00000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x20a00000 0x100000>; + + uart1: serial@0 { + compatible = "rda,8810pl-uart"; + reg = <0x0 0x1000>; + status = "disabled"; + }; + + uart2: serial@10000 { + compatible = "rda,8810pl-uart"; + reg = <0x10000 0x1000>; + status = "disabled"; + }; + + uart3: serial@90000 { + compatible = "rda,8810pl-uart"; + reg = <0x90000 0x1000>; + status = "disabled"; + }; + }; + + l2: cache-controller@21100000 { + compatible = "arm,pl310-cache"; + reg = <0x21100000 0x1000>; + cache-unified; + cache-level = <2>; + }; +};