From patchwork Tue Oct 8 12:55:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 175485 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp5662699ill; Tue, 8 Oct 2019 05:56:09 -0700 (PDT) X-Google-Smtp-Source: APXvYqwG4RWkql9yJnRf8tCFWs6qiUVpzKDJ3pr5wV81nIW73jeej/fuowIMBh604Qox4wyGyquY X-Received: by 2002:a17:906:95cf:: with SMTP id n15mr28558415ejy.183.1570539369025; Tue, 08 Oct 2019 05:56:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570539369; cv=none; d=google.com; s=arc-20160816; b=hePnX24eKTY2AXS23iOgB9KBf99tfp2p9Sal80HRhilQMVfFZZIEHrZfp1cHYzXAdA ajMqJfeUzOXmyYMdEpfv3JetYaxTPLxQvK0LlNaCLsedlEvkONoCV8Ff5eAsLjw5WjTH 95F4iQ/PbI8NPjFWIYt0R6d9SIBU6Ghz9sT8JNUQnwGMrkbgt3CXN7arz8fEpKT/fWZT EYYrOQ5bxaP0alvwgLMSE64vJg+eqpcr8OvrBwOJeaBwChXOeWMj1CTTdTof6A3kBVdW rRccGRhR4DcJGoGfqnaquWtcw+PWEMFDds6QtwiKg5ZjrUsjpcD3jO7KYKnrQeZhULzf auew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=0tln0NRFdBItHIltiQcebxGnUnAgfgYhStbd62D0/jM=; b=MYGByx2FS+RyI56dEWcQRjoIx8sdGPn1PFMSeDxm2QdRSd7XaNOn4o1AOjPv9XdS1A nsLo5uSfZY9D7U2eu+VqmP1tzW6dty0lj6Hf7zyagp0huqMfh5deEWFwsq/OSNx87e/C 8LmouzZQPbJe+ZJNHp+BYxNEZ3hnob9v8yrfgaQMXG8qNz747AqPqmjG4KNuheq7IoWx 0Xio1y2qjb7waGbsqPuxyl8l5EwfslWZ4XoRlDkJSUkjFBi3+W+kQO4m9WQHWIzaTulo IGfGsMpmalbEfXfHTSHzh/ql1bC0LFClhLUhbI8ROg/RUXiWZH/Cjv5/0SVOvYh6BODs hDWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=j3B7Mmrc; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g5si10344318edb.324.2019.10.08.05.56.08; Tue, 08 Oct 2019 05:56:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=j3B7Mmrc; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730958AbfJHM4F (ORCPT + 8 others); Tue, 8 Oct 2019 08:56:05 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:52458 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730915AbfJHM4F (ORCPT ); Tue, 8 Oct 2019 08:56:05 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x98CtvRK068248; Tue, 8 Oct 2019 07:55:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1570539357; bh=0tln0NRFdBItHIltiQcebxGnUnAgfgYhStbd62D0/jM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=j3B7Mmrc2hm6LY+Jg1ZdhZ8GstURcnTriZXoOLFEzkWhiju3n49A5orRlffcSbzDj gPcTHPj9O0PuqNwXcWTPenfFAuCVrfL0YJV9QugsYVwNSQdMYNVw21OjeEGn5Q1rO7 QpgEMs3nMOuDiSRT5I242SDpq4EzJ8bRCJwq3Nq0= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x98Ctv4C010029 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Oct 2019 07:55:57 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 8 Oct 2019 07:55:56 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 8 Oct 2019 07:55:56 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x98Ctk5B046741; Tue, 8 Oct 2019 07:55:55 -0500 From: Tero Kristo To: , CC: , , , , Subject: [PATCHv8 4/9] soc: ti: omap-prm: add support for denying idle for reset clockdomain Date: Tue, 8 Oct 2019 15:55:39 +0300 Message-ID: <20191008125544.20679-5-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191008125544.20679-1-t-kristo@ti.com> References: <20191008125544.20679-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org TI SoCs hardware reset signals require the parent clockdomain to be in force wakeup mode while de-asserting the reset, otherwise it may never complete. To support this, add pdata hooks to control the clockdomain directly. Signed-off-by: Tero Kristo --- drivers/soc/ti/omap_prm.c | 36 ++++++++++++++++++++++++++-- include/linux/platform_data/ti-prm.h | 21 ++++++++++++++++ 2 files changed, 55 insertions(+), 2 deletions(-) create mode 100644 include/linux/platform_data/ti-prm.h -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index 96fa2aad9b93..3d9393ff67e3 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -16,6 +16,8 @@ #include #include +#include + struct omap_rst_map { s8 rst; s8 st; @@ -24,6 +26,7 @@ struct omap_rst_map { struct omap_prm_data { u32 base; const char *name; + const char *clkdm_name; u16 rstctrl; u16 rstst; const struct omap_rst_map *rstmap; @@ -40,6 +43,8 @@ struct omap_reset_data { struct omap_prm *prm; u32 mask; spinlock_t lock; + struct clockdomain *clkdm; + struct device *dev; }; #define to_omap_reset_data(p) container_of((p), struct omap_reset_data, rcdev) @@ -49,6 +54,7 @@ struct omap_reset_data { #define OMAP_PRM_HAS_RSTCTRL BIT(0) #define OMAP_PRM_HAS_RSTST BIT(1) +#define OMAP_PRM_HAS_NO_CLKDM BIT(2) #define OMAP_PRM_HAS_RESETS (OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_RSTST) @@ -133,6 +139,8 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, int st_bit; bool has_rstst; unsigned long flags; + struct ti_prm_platform_data *pdata = dev_get_platdata(reset->dev); + int ret = 0; has_rstst = reset->prm->data->rstst || (reset->prm->data->flags & OMAP_PRM_HAS_RSTST); @@ -146,6 +154,9 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, writel_relaxed(v, reset->prm->base + reset->prm->data->rstst); } + if (reset->clkdm) + pdata->clkdm_deny_idle(reset->clkdm); + /* de-assert the reset control line */ spin_lock_irqsave(&reset->lock, flags); v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); @@ -154,7 +165,7 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, spin_unlock_irqrestore(&reset->lock, flags); if (!has_rstst) - return 0; + goto exit; /* wait for the status to be set */ ret = readl_relaxed_poll_timeout(reset->prm->base + @@ -165,7 +176,11 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, pr_err("%s: timedout waiting for %s:%lu\n", __func__, reset->prm->data->name, id); - return 0; +exit: + if (reset->clkdm) + pdata->clkdm_allow_idle(reset->clkdm); + + return ret; } static const struct reset_control_ops omap_reset_ops = { @@ -190,6 +205,8 @@ static int omap_prm_reset_init(struct platform_device *pdev, { struct omap_reset_data *reset; const struct omap_rst_map *map; + struct ti_prm_platform_data *pdata = dev_get_platdata(&pdev->dev); + char buf[32]; /* * Check if we have controllable resets. If either rstctrl is non-zero @@ -199,6 +216,11 @@ static int omap_prm_reset_init(struct platform_device *pdev, if (!prm->data->rstctrl && !(prm->data->flags & OMAP_PRM_HAS_RSTCTRL)) return 0; + /* Check if we have the pdata callbacks in place */ + if (!pdata || !pdata->clkdm_lookup || !pdata->clkdm_deny_idle || + !pdata->clkdm_allow_idle) + return -EINVAL; + map = prm->data->rstmap; if (!map) return -EINVAL; @@ -213,10 +235,20 @@ static int omap_prm_reset_init(struct platform_device *pdev, reset->rcdev.nr_resets = OMAP_MAX_RESETS; reset->rcdev.of_xlate = omap_prm_reset_xlate; reset->rcdev.of_reset_n_cells = 1; + reset->dev = &pdev->dev; spin_lock_init(&reset->lock); reset->prm = prm; + sprintf(buf, "%s_clkdm", prm->data->clkdm_name ? prm->data->clkdm_name : + prm->data->name); + + if (!(prm->data->flags & OMAP_PRM_HAS_NO_CLKDM)) { + reset->clkdm = pdata->clkdm_lookup(buf); + if (!reset->clkdm) + return -EINVAL; + } + while (map->rst >= 0) { reset->mask |= BIT(map->rst); map++; diff --git a/include/linux/platform_data/ti-prm.h b/include/linux/platform_data/ti-prm.h new file mode 100644 index 000000000000..28154c3226c2 --- /dev/null +++ b/include/linux/platform_data/ti-prm.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * TI PRM (Power & Reset Manager) platform data + * + * Copyright (C) 2019 Texas Instruments, Inc. + * + * Tero Kristo + */ + +#ifndef _LINUX_PLATFORM_DATA_TI_PRM_H +#define _LINUX_PLATFORM_DATA_TI_PRM_H + +struct clockdomain; + +struct ti_prm_platform_data { + void (*clkdm_deny_idle)(struct clockdomain *clkdm); + void (*clkdm_allow_idle)(struct clockdomain *clkdm); + struct clockdomain * (*clkdm_lookup)(const char *name); +}; + +#endif /* _LINUX_PLATFORM_DATA_TI_PRM_H */